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| 型號(hào)： | WED3DL328V8BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 6 ns, PBGA119 |
| 封裝： | 14 X 22 MM, MO-163, BGA-119 |
| 文件頁(yè)數(shù)： | 1/27頁(yè) |
| 文件大小： | 1195K |
| 代理商： | WED3DL328V8BI |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
8Mx32 SDRAM
53% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
Pinout and Footprint Compatible to SSRAM 119 BGA
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
Clock Frequencies of 133MHZ, 125MHZ and 100MHZ
Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full
Page
Burst Read and Write
Multiple Burst Read and Single Write
Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
119 Pin BGA, JEDEC MO-163
The WED3DL328V is an 8Mx32 Synchronous DRAM
congured as 4x2Mx32. The SDRAM BGA is constructed
with two 8Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 14mm by
22mm, BGA.
The WED3DL328V is an ideal SDRAM wide I/O memory
solution for all high performance, computer applications
which include Network Processors, DSPs and Functional
ASICs.
The WED3DL328V is available in clock speeds of 133MHZ,
125MHZ and 100MHZ. The range of operating frequencies,
programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal ground
and power planes which reduces inductance on the ground
and power pins allowing for improved decoupling and a
reduction in system noise.
*NOTE: Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
PIN DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
DESCRIPTION
A0 – A11 Address Bus
BA0-1
Bank Select Addresses
DQ
Data Bus
CK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS#
Row Address Strobe
CAS#
Column Address Strobe
CE#
Chip Enable
VCC
Power Supply pins, 3.3V
VCCQ
Data Bus Power Supply pins,3.3V
VSS
Ground pins
1
2
3
4
5
6
7
A
VCCQ
NC
BA0
NC
A10
A7
VCCQ
A
B
NC
NC/A12*
CAS#
A11
NC
B
C
NC
BA1
VCC
A9
A8
NC
C
D
DQc
NC
VSS
NC
VSS
NC
DQb
D
E
DQc
VSS
CE#
VSS
DQb
E
F
VCCQ
DQc
VSS
RAS#
VSS
DQb
VCCQ
F
G
DQc
DQMC
NC
DQMB
DQb
G
H
DQc
VSS
CKE
VSS
DQb
H
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
J
K
DQd
VSS
CK
VSS
DQa
K
L
DQd
DQMD
NC
DQMA
DQa
L
M
VCCQ
DQd
VSS
WE#
VSS
DQa
VCCQ
M
N
DQd
VSS
A1
VSS
DQa
N
P
DQd
NC
VSS
A0
VSS
NC
DQa
P
R
NC
A6
NC
VCC
NC
A2
NC
R
T
NC
A5
A4
A3
NC
T
U
VCCQ
NC
VCCQ
U
1
2
3
4
5
6
7
FEATURES
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