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參數(shù)資料
| 型號： | WED416S16030A7SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 398K |
| 代理商： | WED416S16030A7SI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED416S16030A
June 2002 Rev. 0
ECO #15332
DESCRIPTION
The WED416S16030A is 268,435,456 bits of synchro-
nous high data rate DRAM organized as 4 x 4,196,304
words x 16 bits. Synchronous design allows precise
cycle control with the use of system clock. I/O transac-
tions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst lengths and pro-
grammable latencies allow the same device to be use-
ful for a variety of high bandwidth, high performance
memory system applications.
Available in a 54 pin TSOP type II package the
WED416S16030A is tested over the industrial temp
range (-40°C to +85°C) providing a solution for rugged
main memory applications.
4M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
■ Single 3.3V power supply
■ Fully Synchronous to positive Clock Edge
■ Clock Frequency = 133, 125, and 100MHz
■ SDRAM CAS Latency = 2
■ Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
■ DATA Mask Control per byte
■ Auto Refresh (CBR) and Self Refresh
8192 refresh cycles across 64ms
■ Automatic and Controlled Precharge Commands
■ Suspend Mode and Power Down Mode
■ Industrial Temperature Range
FIG. 1
PIN DESCRIPTION
A0-12
Address Inputs
BA0, BA1 Bank Select Addresses
CE
Chip Select
WE
Write Enable
CLK
Clock Input
CKE
Clock Enable
DQ0-15
Data Input/Output
L(U)DQM Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
VDD
Power (3.3V)
VDDQ
Data Output Power
VSS
Ground
VSSQ
Data Output Ground
NC
No Connection
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CE
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
TERMINAL
CONNECTIONS
(T
OP
VEIW)
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