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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED9LC6816V
J anuary 2001
DESCRIPTION
The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline
SRAM and a 4Mx32 Synchronous DRAM array constructed with
one 256K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on
a multilayer laminate substrate. The device is packaged in a 153
lead, 14mm by 22mm, BGA.
The WED9LC6816V provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150, and 133 MHz, allowing the user to develop a fast
external memory for the SSRAM interface port .
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the
SDRAM interface port.
The WED9LC6816V is available in both commercial and industrial
temperature ranges.
256Kx32 SSRAM/4Mx32 SDRAM
External Memory Solution for Texas Instruments TMS320C6000 DSP
FEATURES
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Clock speeds:
SSRAM: 200, 166,150, and 133 MHz
SDRAMs: 125 and 100 MHz
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DSP Memory Solution
Texas Instruments TMS320C6201
Texas Instruments TMS320C6701
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Packaging:
153 pin BGA, JEDEC MO-163
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3.3V Operating supply voltage
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Direct control interface to both the SSRAM and SDRAM ports
on the “C6x”
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Common address and databus
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65% space savings vs. monolithic solution
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Reduced system inductance and capacitance
FIG. 1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
A
DQ
19
DQ
23
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
24
DQ
28
A
B
DQ
18
DQ
22
V
CC
V
SS
SDCE
V
SS
V
CC
DQ
25
DQ
29
B
C
V
CCQ
V
CCQ
V
CC
SDWE
SDA
10
NC
V
CC
V
CCQ
V
CCQ
C
D
DQ
17
DQ
21
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
26
DQ
30
D
E
DQ
16
DQ
20
V
CC
V
SS
SDCLK
V
SS
V
CC
DQ
27
DQ
31
E
F
V
CCQ
V
CCQ
V
CC
V
SS
V
SS
V
SS
V
CC
V
CCQ
V
CCQ
F
G
NC
NC
NC
SDRAS SDCAS
V
SS
A
2
A
4
A
5
G
H
NC
NC
A
8
V
SS
V
SS
NC
A
1
A
3
A
10
H
J
A
6
A
7
A
9
V
SS
V
SS
NC
A
0
A
11
A
12
J
K
A
17
NC / A
18
NC / A
19
V
SS
V
SS
NC
NC
A
13
A
14
K
L
NC
NC
NC
BWE
2
BWE
3
NC
NC
A
15
A
16
L
M
V
CCQ
V
CCQ
V
CC
BWE
0
BWE
1
NC
V
CC
V
CCQ
V
CCQ
M
N
DQ
12
DQ
11
V
CC
V
SS
V
SS
V
SS
V
CC
DQ
4
DQ
0
N
P
DQ
13
DQ
10
V
CC
V
SS
SSCLK
V
SS
V
CC
DQ
5
DQ
1
P
R
V
CCQ
V
CCQ
V
CC
V
SS
V
SS
V
SS
V
CC
V
CCQ
V
CCQ
R
T
DQ
14
DQ
9
V
CC
SSADC SSWE
NC
V
CC
DQ
6
DQ
2
T
U
DQ
15
DQ
8
V
CC
SSOE
SSCE
NC
V
CC
DQ
7
DQ
3
U
1
2
3
4
5
6
7
8
9
TOP VIEW
A
0-17
Address Bus
DQ
0-31
Data Bus
SSCLK
SSRAM Clock
SSADC
SSRAM Address Status Control
SSWE
SSRAM Write Enable
SSOE
SSRAM Output Enable
SDCLK
SDRAM Clock
SDRAS
SDRAM Row Address Strobe
SDCAS
SDRAM Column Address Strobe
SDWE
SDRAM Write Enable
SDA
10
SDRAM Address 10/auto precharge
BWE
0-3
SSRAM Byte Write Enables
SDRAM SDQM 0 - 3
SSCE
Chip Enable SSRAM Device
SDCE
Chip Enable SDRAM Device
V
CC
Power Supply pins, 3.3V
V
CCQ
Data Bus Power Supply pins,
3.3V (2.5V future)
V
SS
Ground
NC
No Connect
PIN DESCRIPTION
Advanced*
*This data sheet describes a product that may or may not be under development and
is subject to change or cancellation without notice.