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參數(shù)資料
| 型號(hào)： | WEDPN4M72V-ESB2 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 4M X 72 SYNCHRONOUS DRAM MODULE, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大小： | 0K |
| 代理商： | WEDPN4M72V-ESB2 |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
March 2004
Rev. 0
PRELIMINARY
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally congured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
4Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125MHz
Package:
219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ± 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 4M x 72
Weight: WEDPN16M64V-XB2X - 2 grams typical
BENEFITS
67% SPACE SAVINGS
Reduced part count
Reduced I/O count
19% I/O Reduction
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
Upgradeable to 8M x 72 density with same footprint
(contact factory for information)
* This product is under development, is not qualied or characterized and is subject to
change without notice.
21
Discrete Approach
S
A
V
I
N
G
S
Area
5 x 265mm2 = 1328mm 2
441mm2
67%
5 x 54 pins = 270 pins
219 Balls
19%
ACTUAL SIZE
22.3
11.9
I/O
Count
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
WEDPN4M72V-XB2X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN4M72V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4Mx72 Synchronous DRAM |
| WEDPN4M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPN8M64V-100B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-100B2I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-100B2M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
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