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參數資料
| 型號： | WEDPN8M64V-100BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 64 SYNCHRONOUS DRAM MODULE, 7 ns, PBGA219 |
| 封裝： | 25 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 194K |
| 代理商： | WEDPN8M64V-100BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M64V-XBX
November 2003 Rev. 13
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 33,554,432-bit banks is organized as 4,096 rows
by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0, BA1 select the bank; A0-11 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architec-
ture to achieve high-speed operation. This architecture is
compatible with the 2
n rule of prefetch architectures, but
it also allows the column address to be changed on ev-
ery clock cycle to achieve a high-speed, fully random ac-
cess. Precharging one bank while accessing one of the
other three banks will hide the precharge cycles and pro-
vide seamless, high-speed, random-access operation.
8Mx64 Synchronous DRAM
FEATURES
■ High Frequency = 100, 125, 133**MHz
■ Package:
219 Plastic Ball Grid Array (PBGA), 25 x 25mm
■ Single 3.3V ±0.3V power supply
■ Unbuffered
■ Fully synchronous; all signals registered on positive
edge of system clock cycle
■ Internal pipelined operation; column address can be
changed every clock cycle
■ Internal banks for hiding row access/precharge
■ Programmable Burst length 1,2,4,8 or full page
■ 4,096 refresh cycles
■ Commercial, Industrial and Military Temperature Ranges
■ Organized as 8M x 64
User Configurable as 2 x 8M x 32 or 4 x 8M x 16
■ Weight: WEDPN8M64V-XBX - 2.5 grams typical
BENEFITS
■ 41% SPACE SAVINGS
■ Reduced part count
■ Low Profile: 2.20 mm (0.087) Max
■ Reduced trace lengths for lower parasitic capacitance
■ Laminate interposer for optimum TCE match
■ Suitable for hi-reliability applications
■ Upgradeable to 16M x 64 density (WEDPN16M64V-XBX)
*
This product is subject to change without notice.
** 133MHz available at commercial (0oC to + 70oC) temperature only.
25
Discrete Approach
S
A
V
I
N
G
S
Area
4 x 265mm2= 1061mm2
625mm2
41%
ACTUAL SIZE
22.3
11.9
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相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPN8M64V-125B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-125B2I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-125B2M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-133B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
| WEDPN8M64V-133B2I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx64 Synchronous DRAM |
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