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參數(shù)資料
型號(hào): WEDPNF8M721V-1210BM
廠商: Electronic Theatre Controls, Inc.
英文描述: 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
中文描述: 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝
文件頁(yè)數(shù): 1/42頁(yè)
文件大小: 1276K
代理商: WEDPNF8M721V-1210BM
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
September 2002 Rev. 3
8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module
Multi-Chip Package
FEATURES
Package:
275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
Commercial, Industrial and Military Temperature Ranges
Weight:
WEDPNF8M721V-XBX - 2.5 grams typical
SDRAM PERFORMANCE FEATURES
Organized as 8M x 72
High Frequency = 100, 125MHz
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
FLASH PERFORMANCE FEATURES
User Configurable as 1Mx8 or 512Kx16
Access Times of 100, 120, 150ns
3.3 Volt for Read and Write Operations
1,000,000 Erase/Program Cycles
Sector Architecture
One 16KByte, two 8KBytes, one 32KByte, and fif
teen 64KBytes in byte mode
One 8K word, two 4K words, one 16K word, and
fifteen 32K word sectors in word mode.
Any combination of sectors can be concurrently
erased. Also supports full chip erase
Boot Code Sector Architecture (Bottom)
Embedded Erase and Program Algorithms
Erase Suspend/Resume
Supports reading data from or programing data to a
sector not being erased
BENEFITS
42% SPACE SAVINGS
Reduced part count
Reduced I/O count
14% I/O Reduction
Suitable for hi-reliability applications
SDRAM Upgradeable to 16M x 72 density (contact
factory for information)
Flash upgradeable to 2M x 8 (or 1M x 16 or 512K x 32)
density
* This data sheet describes a product that may or may not be under
development and s subject to change or cancellation without notice.
ADVANCED*
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