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參數資料
型號: WF2M32I-120HM5
元件分類: PROM
英文描述: 2M X 32 FLASH 5V PROM MODULE, 120 ns, CHIP66
封裝: 1.185 INCH, CERAMIC, HIP-66
文件頁數: 1/14頁
文件大小: 174K
代理商: WF2M32I-120HM5
1
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
HI-RELIABILITY PRODUCT
WF2M32-XXX5
FIG. 1 PIN CONFIGURATION FOR WF2M32-XHX5
PIN DESCRIPTION
I/O0-31
Data Inputs/Outputs
A0-20
Address Inputs
WE1-4
Write Enables
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
I/O8
I/O9
I/O10
A14
A16
A11
A0
A18
I/O0
I/O1
I/O2
WE2
CS2
GND
I/O11
A10
A9
A15
VCC
CS1
A19
I/O3
I/O15
I/O14
I/O13
I/O12
OE
A17
WE1
I/O7
I/O6
I/O5
I/O4
I/O24
I/O25
I/O26
A7
A12
A20
A13
A8
I/O16
I/O17
I/O18
VCC
CS4
WE4
I/O27
A4
A5
A6
WE3
CS3
GND
I/O19
I/O31
I/O30
I/O29
I/O28
A1
A2
A3
I/O23
I/O22
I/O21
I/O20
11
22
33
44
55
66
1
12
23
34
45
56
TOP VIEW
BLOCK DIAGRAM
2M x 8
8
I/O 0-7
WE CS
1
2M x 8
8
I/O 8-15
WE CS
2
2M x 8
8
I/O 16-23
WE CS
3
2M x 8
8
I/O 24-31
WE CS
4
A 0- 20
OE
2Mx32 5V FLASH MODULE, SMD 5962-97531 (pending) PRELIMINARY*
s Commercial, Industrial, and Military Temperature Ranges
s 5 Volt Read and Write. 5V
± 10% Supply.
s Low Power CMOS
s Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
s Supports reading or programming data to a sector not being
erased.
s RESET pin resets internal state machine to the read mode.
s Built in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5
Application Note.
FEATURES
s Access Time of 90, 120, 150ns
s Packaging:
66 pin, PGA Type, 1.185" square, Hermetic Ceramic HIP
(Package 401).
68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square
(Package 510) 3.56mm (0.140") height. Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3)
s Sector Architecture
32 equal size sectors of 64KBytes per each 2Mx8 chip
Any combination of sectors can be erased. Also supports
full chip erase.
s Minimum 100,000 Write/Erase Cycles Minimum
s Organized as 2Mx32
RESET internally tied to Vcc in the HIP package for this pin configuration. See
Alternate Pin Configuration with RESET tied to pin 12 for system control of
reset (Fig. 10, page 11)
October 1999 Rev.3
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