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參數資料
| 型號： | WF4M16-90DTM5A |
| 英文描述： | 2x2Mx16 5V FLASH MODULE |
| 中文描述： | 2x2Mx16 5V的閃存模塊 |
| 文件頁數： | 1/11頁 |
| 文件大?。?/td> | 138K |
| 代理商： | WF4M16-90DTM5A |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WF4M16-XDTX5
November 1999 Rev.3
2x2Mx16 5V FLASH MODULE
ADVANCED*
I
Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
I
Supports reading or programmng data to a sector not being
erased.
I
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
I
RESET pin resets internal state machine to the read mode.
I
Ready/Busy (RY/BY) output for direction of programor erase
cycle completion.
*
Ths data sheet describes a product that may or may not be under
development andis subect to change or cancellationwithout notice.
Note: For programmng informationrefer to FlashProgrammng 16M5
AppicationNote.
FEATURES
I
Access Time of 90, 120, 150ns
I
Packaging:
56 Lead, Hermetic Ceramc, 0.520" CSOP (Package 213).
Fits standard 56 SSOP footprint.
I
Sector Architecture
32 equal size sectors of 64KBytes per each 2Mx8 chip
Any combination of sectors can be erased. Also supports
full chip erase.
I
Minimum100,000 Write/Erase Cycles Minimum
I
Organized as two banks of 2Mx16; User Configurable as
4 x 2Mx8
I
Commercial, Industrial, and Military Temperature Ranges
I
5 Volt Read and Write. 5V
±
10% Supply.
I
Low Power CMOS
FIG. 1
PIN CONFIGURATION FOR WF4M16-XDTX5
BLOCK DIAGRAM
TOP VIEW
56 CSOP
PIN DESCRIPTION
I/O
0-15
Data Inputs/Outputs
A
0-20
Address Inputs
WE
Write Enable
CS
1-4
Chip Selects
OE
Output Enable
V
CC
Power Supply
GND
Ground
RY/BY
Ready/Busy
RESET
Reset
I/O
0-7
CS
1
CS
2
CS
3
CS
4
I/O
8-15
A
0-20
RY/BY
OE
REWE
2M x 8
2M x 8
2M x 8
2M x 8
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS
1
and CS
3
control the same data bus. Reads cannot be done with CS
1
and CS
3
both active. CS
2
and CS
4
control the same data bus. Reads
cannot be done with CS
2
and CS
4
both active.
3. Address compatible with Intel 2M8 56 SSOP.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
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