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參數(shù)資料
| 型號： | WF4M32-XXX5 |
| 英文描述： | 4Mx32 5V FLASH MODULE |
| 中文描述： | 4Mx32 5V的閃存模塊 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 456K |
| 代理商： | WF4M32-XXX5 |
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WF4M32-XXX5
PRELIMINARY*
June 2004
Rev. 6
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
RESET#
CS
2#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1#
A
19
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
WE#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
V
CC
CS
4#
NC
I/O
27
A
4
A
5
A
6
A20
CS
3#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
FIGURE 1 – PIN CONFIGURATION FOR WF4M32-XH2X5
Top View
4Mx32 5V FLASH MODULE
FEATURES
Access Times of 100, 120, 150ns
Packaging:
66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
68 lead, 40mm Low Profile CQFP (Package
502), 3.5mm (0.140") height.
68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990CQFJ
footprint (Fig. 3)
Sector Architecture
32 equal size sectors of 64KBytes per each 2Mx8
chip
Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 4Mx32
Block Diagram
User configurable as 2x4Mx16 or 4x4Mx8 in HIP
and G4T packages.
Commercial, Industrial, and Military Tem per a ure
Ranges
5 Volt Read and Write. 5V ± 10% Sup ply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle com ple ion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
I/O
0-7
CS1#
CS2#
CS3#
CS4#
I/O
8-15
I/O
16-23
I/O
24-31
OE#
WE#
A
0-20
A
21
2M
x 8
2M x 8
2M
x 8
2M x 8
2M
x 8
2Mx 8
2M
x 8
2M x 8
RESET#
PIN DESCRIPTION
I/O
0-31
A
0-21
WE#
CS
1-4
#
OE#
V
CC
V
SS
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
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