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參數資料
型號: WS1M8-55FMA
元件分類: SRAM
英文描述: 1M X 8 STANDARD SRAM, 55 ns, CDFP36
封裝: CERAMIC, FP-36
文件頁數: 1/6頁
文件大小: 162K
代理商: WS1M8-55FMA
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WS1M8-XXX
2x512Kx8 DUALITHIC SRAM
FEATURES
s Access Times 17, 20, 25, 35, 45, 55ns
s Revolutionary, Center Power/Ground Pinout
s Packaging:
32 pin, Hermetic Ceramic DIP (Package 300)
36 lead Ceramic SOJ (Package 100)
36 lead Ceramic Flatpack (Package 226)
October 2000 Rev. 4
36 CSOJ
36 FLATPACK
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CS1
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
CS2
BLOCK DIAGRAM
512K x 8
A 0-18
OE
WE
CS 1
CS 2
I/O 0-7
(1)
PIN CONFIGURATION FOR WS1M8-XDJX
AND WS1M8-XFX
A0-18
Address Inputs
I/O0-7
Data Input/Output
CS1-2
Chip Selects
OE
Output Enable
WE
Write Enable
VCC
+5.0V Power
GND
Ground
PIN DESCRIPTION
NOTE:
1. CS1 and CS2 are used to select the lower and upper 512Kx8 of the device. CS1 and CS2 must not be enabled at the same time.
s Organized as two banks of 512Kx8
s Commercial, Industrial and Military Temperature Ranges
s 5 Volt Power Supply
s Low Power CMOS
s TTL Compatible Inputs and Outputs
PIN CONFIGURATION FOR WS1M8-XCX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
32 DIP
TOP VIEW
BLOCK DIAGRAM
512K x 8
A 0-18
WE
CS 1
CS 2
I/O 0-7
(1)
A0-18
Address Inputs
I/O0-7
Data Input/Output
CS1-2
Chip Selects
WE
Write Enable
VCC
+5.0V Power
GND
Ground
PIN DESCRIPTION
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