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參數資料
| 型號： | X25169S8I-2.7 |
| 英文描述： | V CC Supervisory Circuit w/Serial E 2 PROM |
| 中文描述： | V CC的監控電路瓦特/ 2 PROM的串行首頁 |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 73K |
| 代理商： | X25169S8I-2.7 |
7032 -1.1 6/17/97 T1/C0/D0 SH
Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
64K
32K
16K
X25648/49,
X25328/29,
X25168/69
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
V
CC
Supervisory Circuit w/Serial E
2
PROM
FEATURES
Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
Save Critical Data With Block Lock
—Block Lock
Protect 0, 1/4, 1/2 or all of
Serial E
PROM Memory Array
In Circuit Programmable ROM Mode
Long Battery Life With Low Power Consumption
—<1
μ
A Max Standby Current
—<5mA Max Active Current during Write
—<400
μ
A Max Active Current during Read
1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
2MHz Clock Rate
Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
SPI Modes (0,0 & 1,1)
Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
High Reliability
Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
TM
Protection
TM
2
DESCRIPTION
These devices combines two popular functions, Supply
Voltage Supervision and Serial E
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
2
PROM Memory in one
The user’s system is protected from low voltage condi-
tions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E
PROM array with Xicor’s Block Lock
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
2
TM
Protection. The
The device utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
TM
cell,
BLOCK DIAGRAM
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
LOW
VOLTAGE
SENSE
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
SERIAL
E
PROM
ARRAY
2
HIGH
VOLTAGE
CONTROL
SI
SO
SCK
CS
RESET/RESET
V
CC
WP
7036 FRM 01
32
8
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相關代理商/技術參數 |
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