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參數資料
| 型號： | X25F128SI-5 |
| 英文描述： | SerialFlash⑩ Memory With Block Lock⑩ Protection |
| 中文描述： | SerialFlash⑩內存區塊可鎖定的⑩保護 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 61K |
| 代理商： | X25F128SI-5 |
X25F128
1
SerialFlash and Block Lock Protection are trademarks of Xicor, Inc.
SerialFlash Memory With Block Lock Protection
FEATURES
1MHz Clock Rate
SPI Serial Interface
16K X 8 Bits
—32 Byte Small Sector Program Mode
Low Power CMOS
—<1
μ
A Standby Current
—<5mA Active Current
1.8V – 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
Block Lock Protection
—Protect 1/4, 1/2 or all of E
2
PROM Array
Built-in Inadvertent Program Protection
—Power-Up/Power-Down protection circuitry
—Program Enable Latch
—Program Protect Pin
Self-Timed Program Cycle
—5ms Program Cycle Time (Maximum)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
16-Lead 150 mil SOIC Package
FUNCTIONAL DIAGRAM
Xicor, Inc. 1995, 1996 Patents Pending
6829-1.9 4/7/97 T3/C0/D0 SH
Characteristics subject to change without notice
6829 ILL F01.1
COMMAND
DECODE
AND CONTROL
LOGIC
X
DECODE
LOGIC
MEMORY
ARRAY
SI
SO
CS
HOLD
STATUS
REGISTER
PROGRAMMING
CONTROL LOGIC
PP
HIGH VOLTAGE
CONTROL
SECTOR DECODE LOGIC
32
8
DATA REGISTER
SCK
DESCRIPTION
The X25F128 is a 131,072-bit CMOS SerialFlash
memory, internally organized 16K X 8. It features a
“Univolt” Program and Read voltage, Serial Peripheral
Interface (SPI), and software protocol allowing operation
on a simple three-wire bus. The bus signals are a clock
input (SCK), plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a chip
select (
CS
) input, allowing any number of devices to
share the same bus.
The X25F128 also features two additional inputs that
provide the end user with added flexibility. By asserting
the
HOLD
input, the X25F128 will ignore transitions on
its inputs, thus allowing the host to service higher priority
interrupts. The
PP
input can be used as a hardwire input
to the X25F128 disabling all program attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering 0, 1/4, 1/2, or all of the
memory.
The X25F128 utilizes Xicor’s proprietary flash cell, pro-
viding a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
X25F128
16K x 8 Bits
A
PPLICATION
N
OTE
A V A I L A B L E
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