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參數資料
型號: X28LV010T-70
元件分類: EEPROM
英文描述: 128Kx8 EEPROM
中文描述: 128Kx8 EEPROM
文件頁數: 1/18頁
文件大小: 141K
代理商: X28LV010T-70
2000-4003 9/6/00 EP
Xicor, Inc. 2000 Patents Pending
Characteristics subject to change without notice.
1 of 18
1M
X28LV010
128K x 8 Bit
3.3 Volt, Byte Alterable E
2
PROM
FEATURES
Access Time: 70, 90, 120, 150ns
Simple Byte and Page Write
—Single 3.3V±10% supply
—No external high voltages or V
—Self-timed
no erase before write
no complex programming algorithms
no overerase problem
Low Power CMOS
—Active: 20mA
—Standby: 20μA
Software Data Protection
—Protects data against system level inadvertant
writes
High Speed Page Write Capability
Highly Reliable Direct Write
—Endurance: 100,000 write cycles
—Data retention: 100 Years
Early End of Write Detection
—DATA polling
—Toggle bit polling
PP
control circuits
Cell
DESCRIPTION
The Xicor X28LV010 is a 128K x 8 E
cated with Xicor's proprietary, high performance, float-
ing
gate
CMOS
technology.
programmable non-volatile memories the X28LV010
requires a single voltage supply. The X28LV010 fea-
tures the JEDEC approved pinout for byte-wide memo-
ries, compatible with industry standard EPROMs.
2
PROM, fabri-
Like
all
Xicor
The X28LV010 supports a 256-byte page write opera-
tion, effectively providing a 12μs/byte write cycle and
enabling the entire memory to be typically written in
less than 2.5 seconds. The X28LV010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28LV010 supports
Software Data Protection option.
Xicor E
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
2
PROMs are designed and tested for applica-
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Control
Logic and
Timing
1M-Bit
E
2
PROM
Array
I/O
0
–I/O
7
Data Inputs/Outputs
CE
OE
V
CC
V
SS
A
8
–A
16
WE
A
0
–A
7
Y Buffers
Latches and
Decoder
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