
1
FN8117.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PRELIMINARY
X40420, X40421
4kbit EEPROM
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—V
TRIP2
programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor two voltages or detect power fail
Battery switch backup
V
OUT
: 5mA to 50mA from V
CC
; or 250μA from
V
BATT
Fault detection register
Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
Debounced manual reset input
Low power CMOS
—25μA typical standby current, watchdog on
—6μA typical standby current, watchdog off
—1μA typical battery current in backup mode
4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
400kHz 2-wire interface
2.7V to 5.5V power supply operation
Available packages
—14 Ld SOIC, TSSOP
Pb-free plus anneal available (RoHS compliant)
Monitor voltages: 5V to 1.6V
Memory security
Battery switch backup
V
OUT
5mA to 50mA
APPLICATIONS
Communications equipment
—Routers, hubs, switches
—Disk arrays
Industrial systems
—Process control
—Intelligent instrumentation
Computer systems
—Desktop computers
—Network servers
X40420, X40421
Standard V
TRIP1
Level
4.6V (±1%)
4.6V (±1%)
2.9V(±1.7%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
Lock
protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
Standard V
TRIP2
Level
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
Suffix
-A
-B
-C
V2FAIL
WDO
MR
LOWLINE
RESET
X40421
RESET
X40420
+
-
V2Logic
V
TRIP2
FaRegister
Status
Register
EEPROM
Array
Data
Register
Command
Decode Test
& Control
Logic
MPower-on,
LoReset
Generation
V
CC
Monitor
V2MON
SDA
WP
SCL
V
CC
(V1MON)
Watchdog
and
Reset Logic
System
Battery
Switch
V
BATT
V
OUT
BATT-ON
+
-
V
TRIP1
V
OUT
V
OUT
V
OUT
Data Sheet
May 25, 2006