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參數資料
| 型號： | X68257SM |
| 英文描述： | E2 Micro-Peripheral |
| 中文描述： | E2微型外設 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 70K |
| 代理商： | X68257SM |
X68257
1
Xicor, Inc. 1994, 1995, 1996 Patents Pending
6539-1.7 9/16/96 T0/C1/D2 SH
Characteristics subject to change without notice
E
2
Micro-Peripheral
256K
X68257
32,768 x 8 Bit
DESCRIPTION
The X68257 is an 32K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FEATURES
Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family
High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500
μ
A Standby Maximum
Software Data Protection
Toggle Bit Polling
—Early End of Write Detection
Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
28-Lead PDIP Package
28-Lead SOIC Package
32-Lead PLCC Package
FUNCTIONAL DIAGRAM
CONTROL
LOGIC
SOFTWARE
DATA
PROTECT
CE, CE
R/W
E
SEL
A8–A14
AS
L
A
T
C
H
E
S
D
E
C
O
D
E
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
X
32K x 8
E2PROM
6539 ILL F02.2
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