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參數資料
| 型號： | XC17256DDD8M |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | QPRO Family of XC1700D QML Configuration PROMs |
| 中文描述： | 256K X 1 CONFIGURATION MEMORY, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 103K |
| 代理商： | XC17256DDD8M |
DS070 (v2.1) June 1, 2000
Product Specification
1-800-255-77781
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing.)
Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Low-power CMOS EPROM process
Available in 5V version only
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1700D QPRO family of configuration PROMs pro-
vide an easy-to-use, cost-effective method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
0
QPRO Family of XC1700D QML
Configuration PROMs
DS070 (v2.1) June 1, 2000
0
2
Product Specification
R
Figure 1:
Simplified Block Diagram (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC
VPP
GND
DS027_01_021500
TC
OE
or
RESET/
OE/
RESET
CEO
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