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參數資料
型號: XC1765E
廠商: Xilinx, Inc.
英文描述: Configuration PROMs(配置PROM)
中文描述: 配置PROM的(配置可編程)
文件頁數: 1/4頁
文件大小: 71K
代理商: XC1765E
XAPP161 (v2.0) February 17, 2000
1-800-255-7778
1
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
. All other trademarks and registered trademarks are the property of their respective owners.
Summary
Designing a board with Xilinx PROMs is advantageous because migration between XC1700
and XC18V00 series devices is simple. This application note discusses two migration paths:
XC1700 designs upgrading to XC18V00, and XC18V00 designs migrating to XC1700 for
production-stable cost reductions. The topics discussed are pin-out compatibility, power and
ground connections, and boundary-scan chain integrity.
Introduction
The XC1700 series of OTP (one-time programmable) configuration SPROMs is a popular
choice for FPGA configuration. The XC18V00 series of PROMs accommodates the serial
download method of the XC1700 series along with Express and SelectMAP mode parallel-load
innovations. The XC18V00 devices also offer full IEEE Std 1149.1 boundary-scan (JTAG)
support allowing in-system PROM programming and board level testing via the TAP port. In
design environments where in-system reprogrammability is a desired feature, the XC18V00
series of PROMs is the best solution.
Upgrading from the XC1700 family to the XC18V00 family is beneficial to system designers
using the newer configuration modes, boundary-scan testing, or PROM re-programmability.
The system designer may also choose to replace a XC18V00 family device with a XC1700
device for production-stable cost reductions.
Pinout
Compatibility
The XC1700 pinout is a subset of the XC18V00 pinout for specific packages (
Table 1
). The
footprint of a XC1700 device is not compatible with the XC18V00 in a PLCC 20-pin package. All
other available packages are compatible: VQFP 44-pin, PLCC 44-pin, and SOIC 20-pin.
Table 1
shows all XC18V00 specific pins (D7 to D1, VCCO, TCK, TMS, TDI, TDO, CF)
corresponding to no-connect pins on XC1700 devices. These additional signals can be safely
connected to the no-connect pins on a design using the XC1700.
The RESET polarity on the XC18V00 is active low and is not programmable. This will not be an
issue when used with Xilinx FPGAs because the RESET signal on Xilinx FPGAs is always
active Low.
Application Note: XC1700, XC18V00
XAPP161 (v2.0) February 17, 2000
XC1700 and XC18V00 Design Migration
Considerations
Author: Chris Borrelli
R
Table 1:
Pinout Comparison of XC1700 and XC18V00
XC1700 Pinout
PC44
XC18V00 Pinout
PC44
Pin
1
2
3
4
5
6
7
VQ44
SO20
DATA
VQ44
SO20
D0/DATA
D2
CLK
TDI
TMS
TCK
D4, CF
1
DATA
GND
D0/DATA
GND
D2
CLK
CLK
TDI
CLK
TMS
GND
TCK
相關PDF資料
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XC17S10 Spartan Family of One-Time Programmable Configuration PROMs(Spartan系列一次可編程配置PROM)
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相關代理商/技術參數
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