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XC25BS5 Series
PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits
(For Low Frequency Range)
CE, Q0/Q1 Pin Function
C E
FUNCTION
"H"
Q0, Q1 Clock Output
"L"
Stand-by. Output Pin = High Impedance
Open
Stand-by. Output Pin = High Impedance
(VSS Pin Pull-Down Due to IC's Internal Resistor)
GENERAL DESCRIPTION
The XC25BS5 series are high frequency, low power consumption PLL clock generator ICs with divider circuit & multiplier
PLL circuit.
Laser trimming gives the option of being able to select from divider ratios (M) of 1,3
to 2047 and multiplier ratios (N) of 6 to
2047.
Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 3MHz to 30MHz.
Q1
output is selectable from input reference frequency (f0), input reference frequency/2 (f0/2), ground (GND), and comparative
frequency (f0/M). Further, comparative frequencies, within a range of 12KHz to 500KHz, can be obtained by dividing the
reference oscillation.
By halting operation via the CE pin, consumption current can be controlled and output will be one of
high-impedance.
PIN CONFIGURATION
PIN ASSIGNMENT
APPLICATIONS
Crystal oscillation modules
Personal computers
PDAs
Portable audio systems
Various system clocks
FEATURES
Output Frequency : 3MHz ~ 30MHz (Q0=fCLKin
N/M)
Input Frequency (fCLKin)
: 12kHz ~ 35MHz
Divider Ratio (M)
: Selectable from divisions of 1, 3~2047
Multiplier Ratio (N) : Selectable from multiplications of 6~2047
Output
: 3-State
Q1 output selectable from input reference
oscillation, input reference oscillation/2,
GND, comparative frequency.
Operating Voltage Range
: 2.97V ~ 5.5V
Low Power Consumption
: CMOS (stand-by function included)*1
Comparative Frequency
: 12kHz~500kHz
Package
: SOT-26, USP-6B
*1 High output impedance during standby
Environmentally Friendly: EU RoHS Compliant, Pb Free
*The dissipation pad for the USP-6B package
should be solder-plated in recommended mount
pattern and metal masking so as to enhance
mounting strength and heat release.
If the pad needs to be connected to other pins,
it should be connected to the VDD pin.
PIN NUMBER
SOT-26
USP-6B
PIN
NAME
FUNCTION
1
3
CE
Chip Enable
2
VSS
GND
3
1
Q0
PLL Output
4
6
Q1
Reference Oscillation,
Reference Oscillation/2,
GND, or Comparative
Frequency Output
5
VDD
Power Supply
6
4
CLKin
Reference Clock Input
FUNCTION LIST
"H" = High level
"L" = Low level
SOT-26
(TOP VIEW)
1 Q0
2 VSS
3 CE
CLKin 4
VDD 5
Q1 6
USP-6B
(BOTTOM VIEW)
ETR1502_003a