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參數資料
| 型號： | XC2C64A-5QFG48C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC CRII CPLD 64MCRCELL 48QFN |
| 標準包裝： | 260 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 4.6ns |
| 電壓電源 - 內部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數目： | 4 |
| 宏單元數： | 64 |
| 門數： | 1500 |
| 輸入/輸出數： | 37 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 600 (CN2011-ZH PDF) |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E 122-1532-ND - KIT DEVELOPMENT SPARTAN 3ADSP |
| 其它名稱： | 122-1419 |
DS090 (v3.1) September 11, 2008
1
Product Specification
2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
-
Industry’s fastest low power CPLD
-
Densities from 32 to 512 macrocells
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation — 1.5V to 3.3V
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
On-The-Fly Reconfiguration (OTF)
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt trigger input (per pin)
-
Multiple I/O banks on all devices
-
Unsurpassed low power management
DataGATE external signal control
-
Flexible clocking modes
Optional DualEDGE triggered registers
Clock divider (
÷ 2,4,6,8,10,12,14,16)
CoolCLOCK
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Abundant product term clocks, output enables and
set/resets
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional bus-hold, 3-state or weak pullup on select
I/O pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
-
SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
-
Hot pluggable
PLA architecture
-
Superior pinout retention
-
100% product term routability across function block
Wide package availability including fine pitch:
-
Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and QFN packages
-
Pb-free available for all packages
Design entry/verification using Xilinx and industry
standard CAE tools
Free software support for all densities using Xilinx
WebPACK tool
Industry leading nonvolatile 0.18 micron CMOS
process
-
Guaranteed 1,000 program/erase cycles
-
Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE 4.1i WebPACK tool.
Additional details can be found in Further Reading,
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
0
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
00
Product Specification
R
Table 1: CoolRunner-II CPLD Family Parameters
XC2C32A
XC2C64A
XC2C128
XC2C256
XC2C384
XC2C512
Macrocells
32
64
128
256
384
512
Max I/O
33
64
100
184
240
270
TPD (ns)
3.8
4.6
5.7
7.1
TSU (ns)
1.9
2.0
2.4
2.9
2.6
TCO (ns)
3.7
3.9
4.2
4.5
5.8
FSYSTEM1 (MHz)
323
263
244
256
217
179
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