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參數(shù)資料
| 型號(hào)： | XC2S150 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-II 2.5V FPGA(Spartan-II 2.5V現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 的Spartan -Ⅱ2.5V的FPGA的（的Spartan -Ⅱ2.5V的現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 50K |
| 代理商： | XC2S150 |
1
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Introduction
The Spartan
-II 2.5V Field-Programmable Gate Array fam-
ily gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in
Table 1
. System perfor-
mance is supported up to 200 MHz.
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined Virtex-based architec-
ture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits), 16 selectable I/O standards, and four
DLLs. Fast, predictable interconnect means that successive
design iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
Second generation ASIC replacement technology
-
Densities as high as 5,292 logic cells with up to
200,000 system gates
-
Advanced 0.22/0.18 μm 6-layer metal process
-
Streamlined features based on Virtex architecture
-
Unlimited reprogrammability
-
Very low cost
System level features
-
SelectRAM+
hierarchical memory:
·
16 bits/LUT distributed RAM
·
Configurable 4K bit block RAM
·
Fast interfaces to external RAM
-
Fully PCI compliant
-
Low-power segmented routing architecture
-
Full readback ability for verification/observability
-
Dedicated carry logic for high-speed arithmetic
-
Dedicated multiplier support
-
Cascade chain for wide-input functions
-
Abundant registers/latches with enable, set, reset
-
Four dedicated DLLs for advanced clock control
-
Four primary
low-skew
global
clock
distribution
nets
-
IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
-
Low cost packages available in all densities
-
Family footprint compatibility in common packages
-
16 high-performance interface standards
-
Hot swap Compact PCI friendly
-
Zero hold time simplifies system timing
Fully supported by powerful Xilinx development system
-
Foundation Series: Fully integrated software
-
Alliance Series: For use with third-party tools
-
Fully automatic mapping, placement, and routing
0
Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
Preliminary Product Specification
DS001-1 (v2.1) October 31, 2000
0
0
R
Table 1:
Spartan-II FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(C x R)
Total
CLBs
Maximum
Available
User I/O
(1)
Total
Distributed RAM
Bits
Total
Block RAM
Bits
XC2S15
432
6,000 - 15,000
8 x 12
96
86
6,144
16K
XC2S30
972
13,000 - 30,000
12 x 18
216
132
13,824
24K
XC2S50
1,728
23,000 - 50,000
16 x 24
384
176
24,576
32K
XC2S100
2,700
37,000 - 100,000
20 x 30
600
196
38,400
40K
XC2S150
3,888
52,000 - 150,000
24 x 36
864
260
55,296
48K
XC2S200
5,292
71,000 - 200,000
28 x 42
1,176
284
75,264
56K
Notes:
1.
All user I/O counts do not include the four global clock/user input pins. See details in
Table 3, page 3
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC2S15 | Spartan-II 2.5V FPGA(Spartan-II 2.5V現(xiàn)場(chǎng)可編程門陣列) |
| XC2S30 | Spartan-II 2.5V FPGA(Spartan-II 2.5V現(xiàn)場(chǎng)可編程門陣列) |
| XC2V10000 | Virtex-II 1.5V Field-Programmable Gate Arrays(Virtex-II 1.5V 現(xiàn)場(chǎng)可編程門陣列) |
| XC2V2000 | Virtex-II 1.5V Field-Programmable Gate Arrays(Virtex-II 1.5V 現(xiàn)場(chǎng)可編程門陣列) |
| XC2V1500 | Virtex-II 1.5V Field-Programmable Gate Arrays(Virtex-II 1.5V 現(xiàn)場(chǎng)可編程門陣列) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S150-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S150-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S150-5CSG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-5FG256C | 功能描述:IC FPGA 2.5V 864 CLB'S 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
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