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參數資料
型號: XC4000XLASERIES
廠商: Xilinx, Inc.
英文描述: Field Programmable Gate Arrays
中文描述: 現場可編程門陣列
文件頁數: 1/14頁
文件大小: 142K
代理商: XC4000XLASERIES
DS015 (v1.3) October 18, 1999 - Product Specication
6-157
6
XC4000XLA/XV Family Features
Note: XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
System-featured Field-Programmable Gate Arrays
-
Select-RAMTM memory: on-chip ultra-fast RAM with
-
Synchronous write option
-
Dual-port RAM option
-
Flexible function generators and abundant ip-ops
-
Dedicated high-speed carry logic
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal distribution
networks
Flexible Array Architecture
Low-power Segmented Routing Architecture
Systems-oriented Features
-
IEEE 1149.1-compatible boundary scan
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
Unlimited reprogrammability
Read Back Capability
-
Program verication and internal node observability
Electrical Features
XLA Devices Require 3.0 - 3.6 V (VCC)
XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
5.0 V TTL compatible I/O
3.3 V LVTTL, LVCMOS compliant I/O
5.0 V and 3.0 V PCI Compliant I/O
12 mA or 24 mA Current Sink Capability
Safe under All Power-up Sequences
XLA Consumes 40% Less Power than XL
XV Consumes 65% Less Power than XL
Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
Advanced Technology — 5 layer metal, 0.25
m CMOS
process (XV) or 0.35
m CMOS process (XLA)
Highest Performance — System erformance beyond
100 MHz
High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
0
XC4000XLA/XV Field Programmable
Gate Arrays
DS015 (v1.3) October 18, 1999
00*
Product Specification
R
*
Table 1: XC4000XLA Series Field Programmable Gate Arrays
Device
Logic
Cells
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)*
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
User I/O
Required
Congur-
ation Bits
XC4013XLA
1,368
13,000
18,432
10,000 - 30,000
24 x 24
576
1,536
192
393,632
XC4020XLA
1,862
20,000
25,088
13,000 - 40,000
28 x 28
784
2,016
224
521,880
XC4028XLA
2,432
28,000
32,768
18,000 - 50,000
32 x 32
1,024
2,560
256
668,184
XC4036XLA
3,078
36,000
41,472
22,000 - 65,000
36 x 36
1,296
3,168
288
832,528
XC4044XLA
3,800
44,000
51,200
27,000 - 80,000
40 x 40
1,600
3,840
320
1,014,928
XC4052XLA
4,598
52,000
61,952
33,000 - 100,000
44 x 44
1,936
4,576
352
1,215,368
XC4062XLA
5,472
62,000
73,728
40,000 - 130,000
48 x 48
2,304
5,376
384
1,433,864
XC4085XLA
7,448
85,000
100,352
55,000 - 180,000
56 x 56
3,136
7,168
448
1,924,992
XC40110XV
9,728
110,000
131,072
75,000 - 235,000
64 x 64
4,096
9,216
448
2,686,136
XC40150XV
12,312
150,000
165,888
100,000 - 300,000
72 x 72
5,184
11,520
448
3,373,448
XC40200XV
16,758
200,000
225,792
130,000 - 400,000
84 x 84
7,056
15,456
448
4,551,056
XC40250XV
20,102
250,000
270,848
180,000 - 500,000
92 x 92
8,464
18,400
448
5,433,888
* Maximum values of gate range assume 20-30% of CLBs used as RAM
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相關代理商/技術參數
參數描述
XC4000XSERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Gate Arrays
XC4000XV 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000XLA/XV Field Programmable Gate Arrays
XC4000XVSERIES 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays
XC4002 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
XC4002A 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families
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