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參數資料
| 型號： | XC56L307VL150 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 1/4頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MABGA |
| 標準包裝： | 126 |
| 系列： | DSP563xx |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
Freescale Semiconductor
Product Brief Advance Information
DSP56L307PB
Rev. 2, 2/2005
Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
DSP56L307
24-Bit Digital Signal Processor
The Freescale DSP56L307, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations, enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56L307 uses a high-performance, single-clock-cycle-per- instruction
engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access
(DMA) controller (see Figure 1). The DSP56L307 performs at 160 million multiply-accumulates per second (MMACS),
attaining 320 MMACS when the EFCOP is in use. It operates with an internal 160 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
Figure 1. DSP56L307 Block Diagram
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
13
MODD/IRQD
DSP56300
6
16
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM
_
E
B
XM
_
E
B
PM
_
E
B
PI
O
_
EB
Expansion Area
6
5
3
RESET
MODA/IRQA
PINIT/NMI
EXTAL
XTAL
Address
Control
Data
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
× 24 + 56 →56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I - Cache
Control
Memory Expansion Area
DE
Program
RAM
16 K
× 24 bits
X Data
RAM
24 K
× 24 bits
Y Data
RAM
24 K
× 24 bits
External
Address
Bus
Switch
SCI
EFCOP
ESSI
HI08
Triple
Timer
or
15 K
× 24 bits
Instruction
Cache
1024
× 24 bits
Bootstrap
ROM
PCAP
and
OnCE
JTAG
PLL
Clock
Generator
Internal
Data
Bus
Switch
External
Data
Bus
Switch
The DSP56L307 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The EFCOP
can accelerate general
filtering applications, such as
echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
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