- 您現在的位置：買賣IC網 > PDF目錄21981 > XC6SLX45T-3CSG484C (Xilinx Inc)IC FPGA SPARTAN 6 43K 484CSGBGA PDF資料下載
參數資料
| 型號： | XC6SLX45T-3CSG484C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 6/11頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN 6 43K 484CSGBGA |
| 產品培訓模塊： | S6 Family Overview |
| 標準包裝： | 1 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數： | 3411 |
| 邏輯元件/單元數： | 43661 |
| RAM 位總計： | 2138112 |
| 輸入/輸出數： | 296 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應商設備封裝： | 484-CSPBGA |
| 其它名稱： | 122-1756 XC6SLX45T-3CSG484C-ND |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
4
The bitstream configuration information is generated by the ISE software using a program called BitGen. The configuration
process typically executes the following sequence:
Detects power-up (power-on reset) or PROGRAM_B when Low.
Clears the whole configuration memory.
Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.
Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the
DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.
The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods
used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial
flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash.
Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using
Spartan-6 FPGAs in TQG144 and CPG196 packages.
Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in a
single configuration source. The FPGA application controls which configuration to load next and when to load it.
Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes, anti-
cloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.
Readback
Most configuration data can be read back without affecting the system’s operation.
CLBs, Slices, and LUTs
Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical
columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice
contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and
sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.
Expert designers can also instantiate them.
SLICEM
One quarter (25%) of Spartan-6 FPGA slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a
6-input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These
LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register
(SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop
within the CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.
SLICEL
One quarter (25%) of Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the
memory/shift register function.
SLICEX
One half (50%) of Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the
arithmetic carry option and the wide multiplexers.
相關PDF資料 |
PDF描述 |
|---|---|
| EMC40DRAN | CONN EDGECARD 80POS R/A .100 SLD |
| ESC49DRAI | CONN EDGECARD 98POS R/A .100 SLD |
| EMC40DRAH | CONN EDGECARD 80POS R/A .100 SLD |
| ABE40DHRT | CONN CARD EXTEND 80POS 1MM SLD |
| XC6SLX45-L1FGG484I | IC FPGA SPARTAN 6 43K 484FGGBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC6SLX45T-3CSG484I | 功能描述:IC FPGA SPARTAN 6 43K 484CSGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX45T-3FG484C | 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 43661 CELLS 45NM (CMOS) TECHNOLOGY 1. - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 45K 484BGA |
| XC6SLX45T-3FG484I | 功能描述:IC FPGA SPARTAN 6 484FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX45T-3FGG484C | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LXT 標準包裝:60 系列:XP LAB/CLB數:- 邏輯元件/單元數:10000 RAM 位總計:221184 輸入/輸出數:244 門數:- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC6SLX45T-3FGG484I | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 6 LXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
發布緊急采購，3分鐘左右您將得到回復。