參數資料
| 型號： | XC95216-20PQG160C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 216MCRCELL 20NS 160PQFP |
| 產品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標準包裝： | 24 |
| 系列： | XC9500 |
| 可編程類型： | 系統內可編程（最少 10,000 次編程/擦除循環） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數目： | 12 |
| 宏單元數： | 216 |
| 門數： | 4800 |
| 輸入/輸出數： | 133 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 122-1430 |
DS068 (v5.0) May 17, 2013
Product Specification
1
1998–2007, 2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Product Obsolete/Under Obsolescence
Features
10 ns pin-to-pin logic delays on all pins
fCNT to 111 MHz
216 macrocells with 4,800 usable gates
Up to 166 user I/O pins
5V in-system programmable
-
Endurance of 10,000 program/erase cycles
-
Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
-
Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages (Note: 352-pin BGA packages are
being discontinued for this device)
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95216
device.
0
XC95216 In-System
Programmable CPLD
DS068 (v5.0) May 17, 2013
05
Product Specification
R
Figure 1: Typical ICC vs. Frequency for XC95216
Clock Frequency (MHz)
Typical
I
CC
(mA)
050
200
(360)
(500)
(340)
400
600
100
High Performance
Low Power
DS068_01_110101
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相關代理商/技術參數 |
參數描述 |
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| XC95216SERIES | 制造商:XILINX 制造商全稱:XILINX 功能描述:In-System Programmable CPLD |
| XC95288-10BG352C | 功能描述:IC CPLD 288 MCELL C-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數目:24 宏單元數:384 門數:9000 輸入/輸出數:173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-10BG352I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC95288 In-System Programmable CPLD |
| XC95288-10HQ208C | 功能描述:IC CPLD 288 MCELL C-TEMP 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數目:24 宏單元數:384 門數:9000 輸入/輸出數:173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-10HQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC95288 In-System Programmable CPLD |
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