- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄19829 > XC95288XL-10TQG144C (Xilinx Inc)IC CPLD 6.4K 288MCELL 144-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XC95288XL-10TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CPLD 6.4K 288MCELL 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XC9500XL |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 288 |
| 門(mén)數(shù)： | 6400 |
| 輸入/輸出數(shù)： | 117 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 122-1381 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
DS055 (v2.1 April 3, 2007
1
Product Specification
1-800-255-7778
1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Available in small footprint packages
-
144-pin TQFP (117 user I/O pins)
-
208-pin PQFP (168 user I/O pins)
-
256-pin BGA (192 user I/O pins)
-
256-pin FBGA (192 user I/O pins)
-
280-pin CSP (192 user I/O pins)
-
Pb-free available for all packages
Optimized for high-performance 3.3V systems
-
Low power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
-
3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
Fast FLASH technology
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin with local
inversion
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95288XL High Performance
CPLD
DS055 (v2.1 April 3, 2007
05
Product Specification
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL61861ACBZ | IC USB PWR CTRLR 1.5A 8SOIC |
| VI-27Z-CY-F3 | CONVERTER MOD DC/DC 2V 20W |
| VE-240-EV-F1 | CONVERTER MOD DC/DC 5V 150W |
| MAX1792EUA33+T | IC REG LDO 3.3V/ADJ .5A 8-UMAX |
| ISL61861BIBZ | IC USB PWR CTRLR 1.5A 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC95288XL-10TQG144C0962 | 制造商:Xilinx 功能描述:XLXXC95288XL-10TQG144C0962 IC SYSTEMGATE |
| XC95288XL-10TQG144I | 功能描述:IC CPLD 6.4K 288MCELL 144-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500XL 標(biāo)準(zhǔn)包裝:90 系列:ispMACH® 4A 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:4.75 V ~ 5.25 V 邏輯元件/邏輯塊數(shù)目:- 宏單元數(shù):64 門(mén)數(shù):- 輸入/輸出數(shù):48 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) |
| XC95288XL6BG256C | 制造商:Xilinx 功能描述: |
| XC95288XL-6BG256C | 制造商:Xilinx 功能描述:CPLD XC9500XL 6.4K GATES 288 MCRCLLS 208.3MHZ 0.35UM 3.3V 25 - Trays |
| XC95288XL-6BG352C | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Flash Complex PLD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。