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參數(shù)資料
| 型號： | XC95288XV-10TQ144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 2.5V ISP 144-TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 14/May/2007 |
| 標準包裝： | 60 |
| 系列： | XC9500XV |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 2.37 V ~ 2.62 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 288 |
| 門數(shù)： | 6400 |
| 輸入/輸出數(shù)： | 117 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | XC95288XV10TQ144C |
DS050 (v3.0) June 25, 2007
1
Product Specification
2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
u
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC95288XV devices with equivalent XC95288XL
devices in all designs as soon as possible. Recommended
replacements are pin compatible, however require a VCC
change to 3.3V, and a recompile of the design file. In addi-
tion, there is no 1.8V I/O support, and only one output bank
is supported. See XCN07010 for details regarding this dis-
continuation, including device replacement recomendations
for the XC95288XV CPLD.
Features
288 macrocells with 6,400 usable gates
Available in small footprint packages
-
144-pin TQFP (117 user I/O pins)
-
208-pin PQFP (168 user I/O pins)
-
280-pin CSP (192 user I/O pins)
-
256-pin FBGA (192 user I/O pins)
Optimized for high-performance 2.5V systems
-
Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
-
Four separate output banks
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold ciruitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
20 year data retention
-
ESD protection exceeding 2,000V
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
ICCINT (taken from simulation) is:
ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
where:
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
fMAX = max clocking frequency in the device
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95288XV High-Performance
CPLD
DS050 (v3.0) June 25, 2007
05
Product Specification
R
Product Obsolete/Under Obsolescence
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