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參數資料
| 型號： | XCS40XL-4BGG256Q |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 13000 GATES, 217 MHz, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 60K |
| 代理商： | XCS40XL-4BGG256Q |
DS107-1 (v1.4) October 18, 2004
1
Product Specification
1-800-255-7778
2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Introduction
The Spartan-XL 3.3V FPGA Automotive IQ product family
is a high-volume production FPGA solution that delivers all
the key requirements for ASIC replacement up to 40,000
gates. These requirements include high-performance,
on-chip RAM, core solutions, and prices that, in high vol-
ume, approach and in many cases, are equivalent to mask
programmed ASIC devices. By streamlining the Spartan-XL
series feature set, leveraging process technology and
focusing on total cost management, the Spartan-XL series
delivers the key features required by ASIC and other
high-volume logic users while avoiding the initial cost, long
development cycles, and inherent risk of conventional
ASICs.
Features
Guaranteed to meet full electrical specifications over
TJ = –40°C to +125°C
ASIC replacement FPGA for high-volume production
with on-chip RAM
Density up to 1,862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
Broad set of AllianceCORE and LogiCORE
predefined solutions available
Unlimited reprogrammability
System level features
-
On-chip SelectRAM memory
-
Full readback capability for program verification
and internal node observability
-
Dedicated high-speed carry logic
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal networks
-
IEEE 1149.1-compatible Boundary Scan logic
-
Footprint compatibility in common packages
Fully supported by powerful Xilinx development system
-
ISE Foundation Series: Integrated, shrink-wrap
software
-
ISE Alliance Series: Dozens of PC and
workstation third party development systems
supported
-
Fully automatic mapping, placement and routing
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
Enhanced Boundary Scan
Express Mode configuration
Refer to Spartan-XL and Spartan FPGAs complete
data sheet (DS060) for product description, AC and DC
specifications
0
Spartan-XL 3.3V FPGA
Automotive IQ Family:
Introduction and Ordering
DS107-1 (v1.4) October 18, 2004
00
Product Specification
R
Table 1: Spartan-XL Field Programmable Gate Arrays
Device
Logic
Cells
Max System
Gates
Typical
Gate Range
(Logic and RAM)(1)
CLB
Matrix
Total
CLBs
No. of
Flip-flops
Max.
Avail.
User I/O
Total
Distributed
RAM Bits
XCS05XL
238
5,000
2,000-5,000
10 x 10
100
360
77
3,200
XCS10XL
466
10,000
3,000-10,000
14 x 14
196
616
112
6,272
XCS20XL
950
20,000
7,000-20,000
20 x 20
400
1,120
160
12,800
XCS30XL
1,368
30,000
10,000-30,000
24 x 24
576
1,536
192
18,432
XCS40XL
1,862
40,000
13,000-40,000
28 x 28
784
2,016
224
25,088
Notes:
1.
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
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相關代理商/技術參數 |
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| XCS40XL-4CS100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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