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參數資料
| 型號： | XO62CTFHNA1M544 |
| 廠商： | VISHAY DALE |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz, HCMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, ULTRA MINIATURE PACKAGE-4 |
| 文件頁數： | 1/3頁 |
| 文件大?。?/td> | 132K |
| 代理商： | XO62CTFHNA1M544 |
www.vishay.com
38
For technical questions contact: frequency@vishay.com
Document Number: 35058
Revision: 05-Mar-07
XOSM-532
Vishay Dale
Surface Mount Oscillator
FEATURES
5 x 3.2 x 1.3 Miniature Package
Tri-state enable/disable
HCMOS compatible
Tape and Reel
IR Re-flow
2.5 V input voltage
100 % Lead (Pb)-free and RoHS compliant
RoHS
COMPLIANT
The XOSM-532 series is an ultra miniature package clock
oscillator with dimensions 5.0 x 3.2 x 1.3 mm. It is mainly used
in portable PC and telecommunication devices and equipment.
* Include: 25 oC tolerance, operating temperature range, input voltage change, aging, load change, shock and vibration.
DIMENSIONS
in inches [millimeters]
STANDARD ELECTRICAL SPECIFICATIONS
PARAMETER
Frequency Range
Frequency Stability*
Operating Temperature
Storage Temperature Range
Power Supply Voltage
Aging (First Year)
SYMBOL
F
O
CONDITION
XOSM-532
1.544 MHz ~ 100.000 MHz
± 25 ppm, ± 50 ppm, ± 100 ppm
0 oC ~ 70 oC (- 40 oC ~ + 85 oC option)
- 55 oC ~ + 125 oC
2.5 V ± 10 %
± 5 ppm
7 mA Max
8 mA Max
20 mA Max
30 mA Max
40/60 % (45/55 % Option)
6 ns Max
6 ns Max
90 % V
DD
Min
10 % V
DD
Max
30 pF Max (15 pF typ.)
10 ms Max
Pin 1 = H or open.... output active at pin 3
Pin 1 = L..... high impedance at pin 3
All Condition*
T
OPR
T
STG
V
DD
25 oC ± 3 oC
1.544 MHz to 9.999 MHz
10.000 MHz to 34.999 MHz
35.000 MHz to 49.999 MHz
50.000 MHz to 100.000 MHz
At 1/2 V
DD
10 % V
DD
~ 90 % V
DD
90 % V
DD
~ 10 % V
DD
Supply Current
I
DD
Output Symmetry
Rise Time
Fall Time
Sym
T
r
T
f
V
OH
V
OL
Output Voltage
Output Load
Start-up Time
Pin 1, tri-state function
HCMOS Load
Ts
ORDERING INFORMATION
XOSM-532
MODEL
FREQUENCY STABILITY
AA = 0.0025 % (25 ppm)
A = 0.005 % (50 ppm)
B = 0.01 % (100 ppm) Standard
B
R
OTR
Blank = Standard
R = - 40 °C to + 85 °C
E
ENABLE/DISABLE
E = Disable to Tristate
50 M
FREQUENCY/MHz
e4
JEDEC
LEAD (Pb)-FREE
STANDARD
GLOBAL PART NUMBER
MODEL
FREQUENCY
STABILITY
OTR
ENABLE/
DISABLE
PACKAG
E
CODE
OPTIONS
FREQUENCY
***note: A 0.01 μF
b
ypass capacitor sho
u
ld
b
e placed
b
et
w
een
V
DD(Pin4) and G
N
D(Pin2) to minimize po
w
er s
u
pply line noise
X
O
6
2
C
T
E
A
N
A
5
0
M
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