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參數(shù)資料
型號(hào): XR16V2550IM-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 1/46頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR V2550 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16V2550
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
JULY 2012
REV. 1.0.3
GENERAL DESCRIPTION
The XR16V25501 (V2550) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 16 bytes TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16C2550. The V2550 register set
is compatible to the ST16C2550 and the XR16L2550.
It supports Exar’s enhanced features of selectable
FIFO trigger level, automatic hardware (RTS/CTS)
and software flow control, and a complete modem
interface. Onboard registers provide the user with
operational status and data error flags. An internal
loopback capability allows system diagnostics.
Independent programmable baud rate generators are
provided in each channel to select data rates up to 16
Mbps at 3.3 Volt with 4X sampling clock. The V2550
is available in 48-pin TQFP and 32-pin QFN
packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
2.25 to 3.6 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin compatible to ST16C2550, XR16C2550
and XR16L2550 in the 48-TQFP package
Two independent UART channels
Register set compatible to XR16L2550
Data rate of up to 16 Mbps at 3.3 V, and 12.5
Mbps at 2.5 V with 4X sampling rate
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 16 bytes
Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
Device Identification and Revision
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
48-TQFP and 32-QFN packages
FIGURE 1. XR16V2550 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8-bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.25 to 3.6 Volt VCC
GND
* 5 Volt Tolerant Inputs
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
CSB#
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
16 Byte RX FIFO
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