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參數資料
型號: XR17V258IV-0A-EVB
廠商: Exar Corporation
文件頁數: 1/69頁
文件大小: 0K
描述: EVAL BOARD FOR XR17V258 144LQFP
標準包裝: 1
系列: *
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
AUGUST 2010
REV. 1.0.2
GENERAL DESCRIPTION
The XR17V2581 (V258) is a single chip 8-channel
66MHz PCI (Peripheral Component Interconnect)
UART
(Universal
Asynchronous
Receiver and
Transmitter)
solution,
optimized
for
higher
performance and lower power. The V258 device with
its fifth generation register set is designed to meet the
high
bandwidth
and
power
management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family of
products in a 144-pin LQFP package.
The V258 consists of eight independent UART
channels, each with set of configuration and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for all
8-channels to speed up interrupt parsing. The V258
device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787
APPLICATIONS
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Instrumentation
Multi-port RS-232/RS-422/RS-485 Cards
Point-of-Sale Systems
FEATURES
High performance 32-bit 66MHz PCI UART
PCI 3.0 compliance
PCI power management rev. 1.1 compliance
EEPROM interface for PCI configuration
3.3V supply with 5V tolerant non-PCI (serial) inputs
Data read/write burst operation
Global interrupt register for all eight UART channels
Up to 8 Mbps serial data rate
Eight multi-purpose inputs/outputs
A 16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Eight independent UART channels controlled with
16C550 compatible register set
64-byte TX and RX FIFOs with level counters
and programmable trigger levels
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with selectable turn-around delay
Infrared (IrDA 1.0) data encoder/decoder
Programmable data rate with prescaler
FIGURE 1. BLOCK DIAGRAM OF THE XR17V258
G loba l
C o n fig u ra tio n
Re g is te rs
C rysta l Osc/B u ffer
PC I L o ca l
Bu s
Int er fa ce
C onfiguratio n
S p ace
Re g iste rs
Mu lti-pu rp o s e
In puts /O u tputs
16-b it
T ime r/C oun te r
U ART Ch a n ne l 0
64-b yte T X F IF O
6 4-b yte R X FIFO
BR G
IR
ENDE C
TX & RX
UA RT
Re g s
AD [31 :0]
C/BE #[3:0]
PA R
FR AM E #
TR D Y#
IR D Y#
ST O P#
D EVSEL #
ID SEL #
3 3 /6 6 M H z C L K
RS T #
PE RR #
SERR #
PME#
EEC K
EE D I
EED O
EEC S
UA RT C h a n ne l 1
UA RT C h a n ne l 2
UA RT C h a n ne l 3
UA RT C h a n ne l 4
UA RT C h a n ne l 5
UA RT C h a n ne l 6
UA RT C h a n ne l 7
TM R C K
XT AL 2
XT AL 1 /C L K
RX [7:0]
TX [7:0]
RT S #[7:0]
DT R#[7:0]
CTS #[7:0]
DS R #[7:0]
DC D#[7:0]
MP IO [7:0]
R I#[7:0]
EN IR
EE PR O M
In te rfa c e
IN T A#
G loba l
C o n fig u ra tio n
Re g is te rs
G loba l
C o n fig u ra tio n
Re g is te rs
C rysta l Osc/B u ffer
PC I L o ca l
Bu s
Int er fa ce
C onfiguratio n
S p ace
Re g iste rs
Mu lti-pu rp o s e
In puts /O u tputs
Mu lti-pu rp o s e
In puts /O u tputs
16-b it
T ime r/C oun te r
16-b it
T ime r/C oun te r
U ART Ch a n ne l 0
64-b yte T X F IF O
6 4-b yte R X FIFO
BR G
IR
ENDE C
TX & RX
UA RT
Re g s
U ART Ch a n ne l 0
64-b yte T X F IF O
6 4-b yte R X FIFO
BR G
IR
ENDE C
TX & RX
UA RT
Re g s
AD [31 :0]
C/BE #[3:0]
PA R
FR AM E #
TR D Y#
IR D Y#
ST O P#
D EVSEL #
ID SEL #
3 3 /6 6 M H z C L K
RS T #
PE RR #
SERR #
PME#
EEC K
EE D I
EED O
EEC S
UA RT C h a n ne l 1
UA RT C h a n ne l 2
UA RT C h a n ne l 3
UA RT C h a n ne l 4
UA RT C h a n ne l 5
UA RT C h a n ne l 6
UA RT C h a n ne l 7
TM R C K
XT AL 2
XT AL 1 /C L K
RX [7:0]
TX [7:0]
RT S #[7:0]
DT R#[7:0]
CTS #[7:0]
DS R #[7:0]
DC D#[7:0]
MP IO [7:0]
R I#[7:0]
EN IR
EE PR O M
In te rfa c e
EE PR O M
In te rfa c e
IN T A#
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