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參數資料
| 型號： | XRK79892 |
| 廠商： | Exar Corporation |
| 英文描述： | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| 中文描述： | 智能動態時鐘開關PLL時鐘驅動器 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 200K |
| 代理商： | XRK79892 |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
xr
PRELIMINARY
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK79892
JANAUARY 2005
GENERAL DESCRIPTION
REV. P1.0.1
The XRK79892 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
The XRK79892 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
be latched (H). If that CLK is the primary clock, the
device will switch to the good secondary clock and
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32-Lead LQFP Packagin
Pin compatible with MPC9892i
PRODUCT ORDERING INFORMATION
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRK79892
÷4
÷16
PLL
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
MR
PLL_En
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
Dynamic
Switch
Logic
CLK_Selected
INP1Bad
INP0Bad
Man_Override
Alarm_Reset
Sel_CLK
OR
800-1600MHz
P
RODUCT
N
UMBER
P
ACKAGE
T
YPE
O
PERATING
T
EMPERATURE
R
ANGE
XRK79892IQ
32-Lead LQFP
-40°C to +85°C
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