
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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PRELIMINARY
XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
JANUARY 2001
REV. P1.1.0
GENERAL DESCRIPTION
The XRT73L02 Dual Channel E3/DS3/STS-1 Trans-
ceiver IC consists of two fully integrated transmitter
and receiver line transceivers designed for E3, DS3
or SONET STS-1 applications.
Each channel can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Each channel can be con-
figured to operate in a mode/data rate that is indepen-
dent of the other channel.
In the transmit direction, each channel in the
XRT73L02 encodes input data to either B3ZS or
HDB3 format and converts the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT73L02 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line Code Violations.
FEATURES
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Single +3.3V Power Supply
Uses Minimum External components
Operates over -40°C to +85°C Temperature Range
Available in an 80 pin TQFP Thermal Enhanced
package with integral Heat Sink
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
XRT73L02 BLOCK DIAGRAM
AGC/
Equalizer
Serial
Processor
Interface
Peak Detector
LOS Detector
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
SDI
SDO
SClk
CS
REGR
TTIP_(n)
TRing_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
E3_Ch_(n) STS-1/DS3_Ch_(n) Host/HW RLOL_(n) ExClk_(n) RxClkINV
Channel 0
Channel 1
Device
Monitor
Tx
Control
TxLEV_(n)
TxOFF_(n)
DMO_(n)
MTIP_(n)
MRing_(n)
ENDECDIS
Notes: 1. (n) = 0 or 1 for the respective channel.
2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.
LOSTHR_(n)
RxOFF_(n)