- 您現在的位置：買賣IC網 > PDF目錄376462 > XRT79L74 (Exar Corporation) 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC PDF資料下載
參數資料
| 型號： | XRT79L74 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 4 -通道DS3/E3自動柜員機用戶到網絡接口/ Combo IC對購買力平價 |
| 文件頁數： | 1/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | XRT79L74 |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
PRELIMINARY
XRT79L74
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
MARCH 2004
HARDWARE MANUAL
REV. P1.0.0
The XRT79L74 is a four channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controllers and Line Interface Units with Jitter
Attenuators that are designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physi-
cal Medium Dependent and Transmission Conver-
gence sub-layers) interface for the public and private
networks at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L74 includes DS3/E3 Framing, Line
Interface Unit with Jitter Attenuator that supports
mapping of ATM or HDLC framed data. A flexible
parallel microprocessor interface is provided for
configuration and control. Industry standard UTOPIA II
and POS-PHY interface are also provided.
GENERAL FEATURES:
Integrated T3/E3 Line Interface Unit
Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
HDLC Controller that provides the mapping/
extraction
of
either
encapsulated packet from DS3/E3 Frame.
Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
Supports ATM cell or PPP Packet Mapping
Supports M13 and C-Bit Parity Framing Formats
Supports DS3/E3 Clear-Channel Framing.
Includes PRBS Generator and Receiver
Supports Line, Cell, and PLCP Loop-backs
Interfaces to 8 Bit wide Intel, Motorola or PowerPC
Low power 3.3V, 5V Input Tolerant, CMOS
Available in 456 Lead PBGA Package
JTAG Interface
bit
or
byte
mapped
L
INE
I
NTERFACE
U
NIT
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3 Jitter Tolerance Requirements
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
On chip advanced crystal-less Jitter Attenuator
Jitter Attenuator can be selected in Receive or
Transmit paths
16 or 32 bits selectable FIFO size
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
Jitter Attenuator can be disabled
Maximum power consumption 3.1W
DS3/E3 F
RAMER
DS3 framer supports both M13 and C-bit parity.
DS3 framer meets ANSI T1.107 and T1.404
standards.
Detects OOF,LOF,AIS,RDI/FERF alarms.
Generation and Insertion of FEBE on received
parity errors supported.
Automatic insertion of RDI/FERF on alarm status.
E3 framer meets G.832,G.751 standards.
Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
T
RANSMIT
C
ELL
P
ROCESSING
Extracts ATM cells
Supports ATM cell payload scrambling
Maps ATM cells into E3 or DS3 frame
PLCP frame and mapping of ATM cell streams
R
ECEIVE
C
ELL
P
ROCESSING
相關PDF資料 |
PDF描述 |
|---|---|
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設備/調整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環 - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發布緊急采購，3分鐘左右您將得到回復。