
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
PRELIMINARY
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
OCTOBER 2000
REV. P1.0.1
GENERAL DESCRIPTION
The XRT81L27 is an optimized seven-channel, ana-
log, 3.3V, line interface unit, fabricated using low
power CMOS technology. The device contains seven
independent E1 channels, including data and clock
recovery circuits. It is primarily targeted towards the
SDH multiplexers that accomodate TU12 Tributary
Unit Frames. Line cards in these units mutiplex 21 E1
channels into higher SDH rates. Devices with seven
E1 interfaces such as the XRT81L27 provide the
most efficient method of implementing 21-channel
line cards. Each channel performs the driver and re-
ceiver functions necessary to convert bipolar signals
to logical levels and vice versa.
The receiver input accepts transformer or capacitor
coupled signals, while the transmitter is coupled to
the line using a 1:2 step-up transformer. The same
transformer configuration can be used for both bal-
anced 120
and unbalanced 75
interfaces. The
Receiver Loss of Signal Detection is compliant to
G.775 and in Host Mode, the number of zeros re-
ceived before LOS is declared can be increased to
4096 bits. This feature provides the user with the
flexability to implement LOS specifications that re-
quire greater than G.775 requirements
FEATURES
Consists of Seven (7) Independent E1 (CEPT) Line
Interface Units (Transmitter and Receiver)
Generates Transmit Output Pulses that are Compli-
ant with the ITU-T G.703 Pulse Template Require-
ment for 2.048Mbps (E1) Rates
On-Chip Pulse Shaping for both 75
and 120
line
drivers
Receiver Can Either Be Transformer or Capacitive-
Coupled to the Line
Detects and Clears LOS (Loss of Signal) Per ITU-T
G.775
Compliant with the ITU-T G.823 Jitter Tolerance
Requirements
APPLICATIONS
lPDH Multiplexers
SDH Multiplexers
Digital Cross-Connect Systems
DECT (Digital European Cordless Telephone) Base
Stations
CSU/DSU Equipment
F
IGURE
1. B
LOCK
D
IAGRAM
Channe
l 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
TAOS
Channel 7
Timing
Generator
MClk
Encoder
MUX
Timing
Control
TX Pulse
Shaper
TClk
TPOS/TDATA
TNEG/CODE
TTIP
TRing
Remote
Loopback
TClkP
Decoder
Data & Timing
Recovery
Peak
Detector
Receive
Equalizer
Line
Driver
RClk
RPOS
RClkP
RTIP
RRing
LOS
Detect
LOS
Local
Loopback
Serial
Processor
Interface
SDI
SDO
SClk
CS
MUX
Analog
Loopback
RNEG/LCV