
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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PRODUCT BRIEF
XRT84L14
QUAD T1 FRAMER
OCTOBER 2000
REV. A1.0.0
GENERAL DESCRIPTION
The XRT84L14 quad T1/DS1 Framer is a single chip
device which integrates 4 T1 framers and transmitters
for terminating DS1 Signals. Each framer has its own
framing synchronizer and transmit-receive slip
bufffers, and can be independently enabled or dis-
abled as required and can be configured to frame to
the common DS1 signal formats
Each Framer block contains its own Transmit and Re-
ceive T1 Framing function. The Transmit HDLC con-
troller encapsulates contents of the Transmit HDLC
buffers into LAPD Message frames. The Receive
HDLC controller extracts payload content of Receive
LAPD Message frames from the incoming T1 data
stream and writes it into the Receive HDLC buffer.
Each framer also contains a Transmit and Overhead
Data Input port, which permits Data Link Terminal
Equipment direct access to the outbound T1 frames
Likewise, a Receive Overhead output data port per-
mits Data Link Terminal Equipment direct access to
the Data Link bits of the inbound T1 frames.
The XRT84L18 fully meets all of the latest T1 specifi-
cations: ANSI T1.403-1995, ANSI T1.231-1993,
AT&T TR62411 (12-90), AT&T TR54016 and
TR62411, and ITU G-703, G.704, G706 and G.733.
Extensive test and diagnostic functions include Loop-
backs, Boundary scan, Pseudo Random bit se-
quence (PRBS) test pattern generation, Performance
Monitor,
Bit Error Rate (BER) meter, and forced error
insertion.
FEATURES
Four independent, full duplex DS1 Tx and Rx
Framer
Two 512-bit (two-frame) elastic store, PCM frame
slip buffers (FIFO) on TX and Rx
Provides up to 8.192 MHz asynchronous back plane
connections with jitter and wander attenuation
Supports input PCM and signaling data from 1.544
to 8.192 MHz. Also supports 4-channel multiplexed
12.352/16.384 Mbit/s on the back plane bus
Programmable output clocks for Fractional T1
Supports channel associated signaling (CAS)
Supports Common-channel and ISDN Primary Rate
Interface (ISDN PRI) signaling
Integrated HDLC controller with two 96-byte Transmit
HDLC buffers and two 96-byte Receive HDLC buffers
Timeslot assignable HDLC
Programmable Interrupt output pin
Supports programmed I/O, Burst and DMA modes of
Read-Write access
Facilitates Inverse Multiplexing for ATM
Extracts and inserts robbed bit signaling (RBS)
F
IGURE
1. 84L14 S
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PRBS
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Analyser
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External Data
Link Controller
Rx Encoder
LIU
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