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參數資料
型號: XRT86VL3X_07
廠商: Exar Corporation
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數: 1/153頁
文件大?。?/td> 1316K
代理商: XRT86VL3X_07
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT86VL3x
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
JANUARY 2007
REV. 1.2.2
GENERAL DESCRIPTION
The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s
DS1/E1/J1 framer and LIU integrated solution
featuring R
3
technology (Relayless, Reconfigurable,
Redundancy) that comes in a 2-channel, 4-channel,
or 8-channel package. The physical interface is
optimized with internal impedance, and with the
patented pad structure, the XRT86VL3x provides
protection from power failures and hot swapping.
The XRT86VL3x contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VL3x fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor,
Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
F
IGURE
1. XRT86VL3
X
N-C
HANNEL
DS1 (T1/E1/J1) F
RAMER
/LIU C
OMBO
Performance
Monitor
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
LIU &
Loopback
Control
DMA
Interface
Signaling &
Alarms
JTAG
WR
ALE_AS
RD
RDY_DTACK
μ
P
Select
A[14:0]
D[7:0]
Microprocessor
Interface
4
3
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
S
2-Frame
Slip Buffer
Elastic Store
Tx Serial
Data In
Tx LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx LIU
Interface
Rx Framer
Rx Serial
Data Out
RTIP
RRING
TTIP
TRING
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
XRT86VL3x
1 of N-channels
Tx Framer
LLB
LB
System (Terminal) Side
Line Side
1:1 Turns Ratio
1:2 Turns Ratio
Memory
Intel/Motorola μP
Configuration, Control &
Status Monitor
RxLOS
TxON
INT
相關PDF資料
PDF描述
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
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