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參數資料
| 型號： | XRT95L53 |
| 廠商： | EXAR CORP |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA780 |
| 封裝： | PLASTIC, BGA-780 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 63K |
| 代理商： | XRT95L53 |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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PRODUCT BRIEF
XRT95L53 EXtendAR-48M
OC-48 ETHERNET/SONET MULTI-SERVICE FRAMER PROCESSOR
FEBRUARY 2005
GENERAL DESCRIPTION
REV.
P
1.0.0
EXtendar 48M (XRT95L53) is a highly integrated OC-
48/STM-16, Quad OC-12/STM-4 & OC-3/STM-1
Multi-protocol
Framer
processor.
combines standard OC-48/STM-16, Quad OC-12/
STM-4, OC-3/STM-1 SONET framer functions with a
flexible packet interface as well as a range of framing
and encapsulation techniques integrated on a single
chip. EXtendar 48M supports Generic Framing
Procedure (GFP) in combination with Virtual
Concatenation & LCAS, LAPS, POS, ATM and DS3
capabilities configurable on a per-channel basis.
EXtendar 48M is the industry's first device to
integrate 48 DS3/Fractional DS3 framers on a single
chip. EXtendar 48M, in addition to the SONET OC-
48/OC-12/OC-3 interfaces, supports OIF compliant
SPI-3 interface with optional support for Exar's
proprietary G-header interface. Using this industry
first G-header interface, EXtendar 48M provides
framing and encapsulation support for RPR, MPLS or
proprietary client data that need to be transported
over SONET. The unique combination of flexible
packet framing and encapsulation features combined
with optimal SONET transport capabilities make
EXtendar 48M an ideal solution for Multi-service
SONET transport, Core as well as DWDM systems.
This
device
APPLICATIONS
Multi-Service Provisioning Platforms (MSPPs)
SONET/SDH add/drop and terminal multiplexers
Ethernet Over SONET Platforms (MTU/MDU)
L2/L3 Switches & Routers
KEY FEATURES
System-side Interfaces
■
Single OIF compliant SPI-3 interface with
optional support for G-header interface
Serdes
bit@622Mhz)
Line-side Interfaces
■
Working and protect OC-48/STM-16 Serdes
Interfaces (4-bit@622Mhz)
- Supports TFI-5 interface
OC-12/STM-4/OC-3/STM-1
Interfaces (4x1-bit@622Mhz/155Mhz)
Support for flexible mapping of client data on a per
channel basis into optimal SONET/SDH payloads
using Frame-based GFP (GFP -F)
Ethernet
data
payloads using GFP
■
OC-12/STM-4
Interface
(4x1-
■
Quad
Serdes
■
Maps
into
SONET/SDH
■
Maps PPP frames into SONET/SDH payloads
using GFP -F
■
Supports GFP mapping of RPR, MPLS or
proprietary client data using the G-header
interface
■
Supports add/drop of client management
frames from/to the microprocessor interface
Supports a G-header interface in order to
effectively map RPR, MPLS or proprietary client
data over SONET
■
Compatible with OIF compliant SPI-3 interface
G-header
capsulation
■
Performs
encapsulation/de-
■
G-header interface can be optionally disabled
Support
for
contiguous
concatenation for higher order paths
pointer-based
■
Supports mapping of Gigabit Ethernet to STS-
48C/AU4-16C, STS12C/AU4-16C or STS3C/
AU4 or STS-1/AU3
Support for a SPI-3 interface with up to 256 logical
sub-channels and individual channel flow control
Support for High Order and Low Order Virtual
concatenation
with
optional
Adjustment Scheme (LCAS)
Link
Capacity
■
Supports flexible mapping of multi-protocol
traffic into standards based high order virtual
concatenation channels of STS-3c-Xv/VC-4-Xv
as well as STS-1-Xv/VC-3-Xv
■
Supports mapping of multi-protocol traffic into
standards
based
concatenation channels of VT6/VT2/VT1.5
low
order
virtual
■
Supports a total of 64 Virtual Concatenation
Groups (VCG's)
■
Supports Link Capacity Adjustment Scheme
per ITU-T G.7042
■
Provides up to 256 ms of differential delay
compensation using external SDRAM interface
Terminates and processes Section, Line and Path
Overhead on OC-48/STM-16, OC-12/STM-4 and
OC-3/STM-1 interfaces
■
Support for extensive performance monitoring
on the SONET/SDH interfaces
Support for on-chip STS-1 cross-connect between
the OC-12 Add/drop interface and the Lineside
interfaces
Support for UPSR and 1+1 Linear Automatic
Protection Switching
PRELIMINARY
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