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參數資料
型號： ZL50418GKG2
廠商： CONEXANT SYSTEMS
元件分類： 網絡接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA553
封裝： 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
文件頁數： 1/155頁
文件大小： 1928K
代理商： ZL50418GKG2
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Integrated Single-Chip 10/100/1000M Ethernet
Switch
Sixteen 10/100 Mbps auto-negotiating Fast Ethernet
(FE) ports with RMII or GPSI (7WS) interface
options per port
Two 10/100/1000M auto-negotiating Gigabit
Ethernet (GE) ports with GMII, TBI, and MII
interface options per port
Operates stand-alone or can be cascaded
Stacking port supports hot swap in managed
configuration
Supports two Frame Data Buffer (FDB) memory
domains (2 MB or 4 MB) with pipelined, sync-burst
SRAM at 100 MHz
Applies centralized shared memory architecture
L2 Switching
MAC address self learning, up to 64K MAC
addresses
Supports port-based and tagged-based VLAN (IEEE
802.1Q)
Supports up to 255 VLANs and IP multicast groups
VLAN tag insertion and stripping selectable on a per
port, per VLAN basis
Supports spanning tree on per-system (IEEE
802.1D/w) or per-VLAN basis (IEEE 802.1s)
Supports IP Multicast with IGMP snooping
High performance packet classification and
switching at full-wire speed
CPU access supports the following interface
options:
8/16-bit ISA interface in managed mode
Serial interface in unmanaged mode, with optional
I2C EEPROM support
Packet Filtering and Port Security
Static address filtering for source and/or destination
MAC
Static MAC address not subject to aging
Secure mode freezes MAC address learning, each
port may independently use this mode
Supports Ethernet multicasting and broadcasting
and flooding control
Supports per-system option to enable flow
control for best effort frames even on QoS-
enabled ports
July 2006
Ordering Information
ZL50418/GKC
553 Pin HSBGA
ZL50418GKG2
553 Pin HSBGA**
**Pb Free Tin/Silver/Copper
-40°C to 85°C
Figure 1 - System Block Diagram
FDB Interface
Frame Data Buffer A
SRAM (1 M / 2 M)
LED
Search
Engine
MCT
Link
Frame Engine
FCB
Management
Module
16 x 10/100M
RMII
Ports 0 - 15
VL
AN
1
MC
T
Frame Data Buffer B
SRAM (1 M / 2 M)
VLAN
1
MCT
GMII/
PCS
Port
24
GMII/
PCS
Port
25
16-bit
Parallel /
Serial
ZL50418
Managed 16-Port 10/100M + 2-Port
10/100/1000M Layer-2 Ethernet Switch
Data Sheet
相關PDF資料
PDF描述
ZL50418/GKC DATACOM, LAN SWITCHING CIRCUIT, PBGA553
ZL50418GKG2 DATACOM, LAN SWITCHING CIRCUIT, PBGA553
ZLW-2-B 1 MHz - 1000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 9.5 dB CONVERSION LOSS-MAX
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