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參數(shù)資料
型號(hào): μ PD431231L
廠商: NEC Corp.
英文描述: 1M-Bit CMOS Synchronous Fast Static RAM(1M CMOS 同步快速靜態(tài)RAM)
中文描述: 100萬位CMOS同步快速靜態(tài)RAM(100萬的CMOS同步快速靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 1/20頁(yè)
文件大小: 156K
代理商: Μ PD431231L
MOS INTEGRATED CIRCUIT
μ
PD431231L
The information in this document is subject to change without notice.
1996
1M-BIT CMOS SYNCHRONOUS FAST SRAM
32K-WORD BY 32-BIT
PIPELINED OPERATION
Document No. M12075EJ4V0DS00 (4th edition)
Date Published June 1998 NS CP(K)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
Description
The
μ
PD431231L is a 32,768-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology
using N-channel four-transistor memory cell.
The
μ
PD431231LGF integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well
as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
The
μ
PD431231LGF is suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
μ
PD431231LGF is packaged in 100-pin plastic TQFP with a 1.4 mm package thickness (LQFP in EIAJ) for high
density and low capacitive loading.
Features
3.3 V (Chip) / 2.5V (I/O) Supply
Synchronous Operation
Internally self-timed Write control
Burst Read / Write: Interleaved Burst and Linear Burst Sequence
Fully Registered Inputs and Outputs for Pipelined operation
All Registers triggered off Positive Clock Edge
2.5 V LVTTL Compatible: All Inputs and Outputs
Fast Clock Access Time: 7 ns (83 MHz), 8 ns (66 MHz)
Asynchronous Output Enable: /G
Burst Sequence Selectable: MODE
Sleep Mode: ZZ (ZZ =O pen or Low: Normal Operation)
Separate Byte Write Enable: /BW1 - /BW4, /BWE and Global Write Enable: /GW
Three Chip Enables for Easy Depth Expansion
Common I/O Using Three State Outputs
Ordering Information
Part number
Access Time
Clock frequency
Package
μ
PD431231LGF-A7
μ
PD431231LGF-A8
7.0 ns
83 MHz
100-pin plastic TQFP (14 x 20 mm)
8.0 ns
66 MHz
100-pin plastic TQFP (14 x 20 mm)
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