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參數資料
| 型號： | μ PD464536L |
| 廠商： | NEC Corp. |
| 英文描述： | 4M-Bit Bi-CMOS Synchronous Fast Static RAM(4M BiCMOS 同步快速靜態RAM) |
| 中文描述： | 4分位的Bi - CMOS同步快速靜態隨機存儲器（4分的BiCMOS同步快速靜態內存） |
| 文件頁數： | 1/24頁 |
| 文件大小： | 166K |
| 代理商： | Μ PD464536L |
1997
MOS INTEGRATED CIRCUIT
μ
PD464518L, 464536L
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
LVTTL INTERFACE
DATA SHEET
The mark
shows major revised points.
Document No. M12079EJ6V0DS00 (6th edition)
Date Published September 1998 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice.
Description
The
μ
PD464518L is a 262,144 words by 18 bits, and the
μ
PD464536L is a 131,072 words by 36 bits synchronous
static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the
μ
PD464518L and
μ
PD464536L a high-speed device. The
μ
PD464518L and
μ
PD464536L are suitable for applications which require high-speed, low voltage, high-density
memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
LVTTL 3.3 V I/O
Register to latch synchronous operation
Single differential clock inputs
Fast clock access time : 8.0 ns / 125 MHz
Single Differential Clock, Registered Input / Latched Output
Asynchronous output enable control : /G
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
Boundary scan (JTAG) IEEE 1149.1 compatible
Single +3.3 V power supply
Ordering Information
Part number
Access time
Clock frequency
Package
μ
PD464518LS1-A8
8.0 ns
125 MHz
119-pin plastic BGA
μ
PD464536LS1-A8
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