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參數資料
| 型號： | 100LVELT22M8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator |
| 中文描述： | DUAL TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8 |
| 封裝： | 3 MM, MO-187, MSOP-8 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 119K |
| 代理商： | 100LVELT22M8 |
2003 Fairchild Semiconductor Corporation
DS500777
www.fairchildsemi.com
January 2003
Revised January 2003
1
100LVELT22
3.3V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential
LVPECL translator operating from a single
+
3.3V supply.
Both outputs of a differential pair should be terminated in
50
to V
CC
- 2.0V even if only one output is being used. If
an output pair is unused both outputs can be left open
(un-terminated).
The 100 series is temperature compensated.
Features
I
Typical propagation delay of 350 ps
I
<
100 ps skew between outputs
I
Max I
CC
of 28 mA at 25
°
C
I
When TTL input is left Open Q output defaults HIGH
I
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
I
Flow through pinout
I
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
I
Moisture Sensitivity Level 1
I
ESD Performance:
Human Body Model
>
2000V
Machine Model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Code
Top Mark
KVT22
KR22
Package Description
Package
Number
M08A
MA08D
100LVELT22M
100LVELT22M8
(Preliminary)
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name
Description
Q
n
, Q
n
D
0
, D
1
V
CC
GND
LVPECL Differential Outputs
LVTTL/LVCMOS Inputs
Positive Supply
Ground
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