
2N6660CSM4
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DOC 7777, ISSUE 2
FEATURES
Faster switching
Low Ciss
Integral Source-Drain Diode
High Input Impedance and High Gain
DESCRIPTION
This enhancement-mode (normally-off) vertical DMOS FET is
ideally suited to a wide range of switching and amplifying
applications where high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Hi-Reliability Military and Space screening options available
N–CHANNEL
ENHANCEMENT MODE
MOSFET
V
DSS
60V
I
D
1.0A
R
DS(on)
3.0
LCC3 PACKAGE (MO-041BA)
(Underside View)
PAD 1 – DRAIN
PAD 3 – SOURCE
PAD 2 – N/C
PAD 4 – GATE
1
2
3
4
5.59 ± 0.13
(0.22 ± 0.005)
0.23
(0.009)
rad.
1.02 ± 0.20
(0.04 ± 0.008)
2.03 ± 0.20
(0.08 ± 0.008)
1.40 ± 0.15
(0.055 ± 0.006)
0.25 ± 0.03
(0.01 ± 0.001)
0.23
(0.009)
min.
1.
27
±
0.
05
(0
.0
5
±
0.
002
)
3.
81
±
0.
13
(0
.15
±
0.
00
5)
0.
64
±
0.
08
(0
.025
±
0.
003)
MECHANICAL DATA
Dimensions in mm (inches)
ABSOLUTE MAXIMUM RATINGS T
CASE = 25°C unless otherwise stated
V
DS
Drain - Source Voltage
60V
I
D
Drain Current
- Continuous (T
C = 25°C)
1.0A
I
DM
Drain Current
- Pulsed (Note 1)
3A
V
GS
Gate - Source Voltage
±20V
P
tot(1)
Total Power Dissipation at T
mounting base ≤ 25°C
3.0W
De-rate Linearly above 25°C
0.020W/°C
P
tot(2)
Total Power Dissipation at T
ambient ≤ 25°C
0.5W
T
j,Tstg
Operating and Storage Junction Temperature Range
-55 to +175°C
THERMAL DATA
R
thj-mb
Thermal Resistance Junction – Mounting base
Max
50
°C/W
NOTES:
1) Repetitive Rating: Pulse Width limited by maximum junction temperature.
2) Pulse Test: Pulse Width ≤ 300S, Duty Cycle , δ 2%