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參數(shù)資料
型號(hào): 2SK4078
廠商: NEC Corp.
英文描述: SWITCHING N-CHANNEL POWER MOS FET
中文描述: 開關(guān)N溝道功率場效應(yīng)晶體管
文件頁數(shù): 2/8頁
文件大小: 182K
代理商: 2SK4078
Data Sheet D18885EJ1V0DS
2
2SK4078
ELECTRICAL CHARACTERISTICS (T
A
= 25
°
C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 40 V, V
GS
= 0 V
1
μ
A
Gate Leakage Current
I
GSS
V
GS
=
±
20 V, V
DS
= 0 V
±
100
nA
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Note
V
GS(off)
V
DS
= 10 V, I
D
= 1 mA
1.5
2.0
2.5
V
| y
fs
|
V
DS
= 10 V, I
D
= 25 A
7.0
S
Drain to Source On-state Resistance
Note
R
DS(on)1
V
GS
= 10 V, I
D
= 25 A
6.3
8.5
m
Ω
R
DS(on)2
V
GS
= 4.5 V, I
D
= 13 A
9.5
14.0
m
Ω
Input Capacitance
C
iss
V
DS
= 10 V,
2300
pF
Output Capacitance
C
oss
V
GS
= 0 V,
360
pF
Reverse Transfer Capacitance
C
rss
f = 1 MHz
220
pF
Turn-on Delay Time
t
d(on)
V
DD
= 20 V, I
D
= 25 A,
12
ns
Rise Time
t
r
V
GS
= 10 V,
15
ns
Turn-off Delay Time
t
d(off)
R
G
= 0
Ω
51
ns
Fall Time
t
f
9
ns
Total Gate Charge
Q
G
V
DD
= 32 V,
45
nC
Gate to Source Charge
Q
GS
V
GS
= 10 V,
7
nC
Gate to Drain Charge
Body Diode Forward Voltage
Note
Q
GD
I
D
= 50 A
13
nC
V
F(S-D)
I
F
= 50 A, V
GS
= 0 V
1.5
V
Reverse Recovery Time
t
rr
I
F
= 50 A, V
GS
= 0 V,
30
ns
Reverse Recovery Charge
Q
rr
di/dt = 100 A/
μ
s
26
nC
Note
Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 3 GATE CHARGE
V
GS
= 20
0 V
PG.
R
G
= 25
Ω
50
Ω
D.U.T.
L
V
DD
PG.
D.U.T.
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
R
G
PG.
I
G
= 2 mA
50
Ω
D.U.T.
R
L
V
DD
I
D
V
DD
I
AS
V
DS
BV
DSS
Starting T
ch
V
GS
0
τ
= 1
s
Duty Cycle
1%
τ
V
GS
Wave Form
DS
Wave Form
V
GS
V
DS
10%
0
0
90%
90%
90%
V
GS
V
DS
t
on
t
off
t
d(on)
t
r
t
d(off)
t
f
10%
10%
μ
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