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參數(shù)資料
| 型號： | 49LF002 |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub |
| 中文描述： | 2兆位/ 3兆/ 4兆位/ 8兆固件集線器 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 412K |
| 代理商： | 49LF002 |
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Advance Information
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
2001 Silicon Storage Technology, Inc.
S71161-06-000
9/01
504
AC CHARACTERISTICS (PP MODE)
TABLE 20: READ CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
270
ns
TRST
RST# High to Row Address Setup
1
s
TAS
R/C# Address Set-up Time
45
ns
TAH
R/C# Address Hold Time
45
ns
TAA
Address Access Time
120
ns
TOE
Output Enable Access Time
60
ns
TOLZ
OE# Low to Active Output
0
ns
TOHZ
OE# High to High-Z Output
35
ns
TOH
Output Hold from Address Change
0
ns
T20.2 504
TABLE 21: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TRST
RST# High to Row Address Setup
1
s
TAS
R/C# Address Setup Time
50
ns
TAH
R/C# Address Hold Time
50
ns
TCWH
R/C# to Write Enable High Time
50
ns
TOES
OE# High Setup Time
20
ns
TOEH
OE# High Hold Time
20
ns
TOEP
OE# to Data# Polling Delay
40
ns
TOET
OE# to Toggle Bit Delay
40
ns
TWP
WE# Pulse Width
100
ns
TWPH
WE# Pulse Width High
100
ns
TDS
Data Setup Time
50
ns
TDH
Data Hold Time
5
ns
TIDA
Software ID Access and Exit Time
150
ns
TBP
Byte Programming Time
20
s
TSE
Sector-Erase Time
25
ms
TBE
Block-Erase Time
25
ms
TSCE
Chip-Erase Time
100
ms
T21.2 504
TABLE 22: RESET TIMING PARAMETERS, VDD =3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TPRST
VDD stable to Reset Low
1
ms
TRSTP
RST# Pulse Width
100
ns
TRSTF
RST# Low to Output Float
48
ns
TRST1
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.
RST# High to Row Address Setup
1
s
TRSTE
RST# Low to reset during Sector-/Block-Erase or Program
10
s
TRSTC
RST# Low to reset during Chip-Erase
50
s
T22.1 504
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