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參數資料
型號: 554HC000249DGR
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, ECL OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁數: 1/14頁
文件大?。?/td> 238K
代理商: 554HC000249DGR
Rev. 0.6 6/07
Copyright 2007 by Silicon Laboratories
Si554
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ
Features
Applications
Description
The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory-programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Four selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
Clock Synthesis
ADC
VDD
CLK+
CLK-
Vc
OE
GND
FS1
FS0
Ordering Information:
Pin Assignments:
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
FS[1]
FS[0]
8
7
REVISION D
相關PDF資料
PDF描述
571ACC000107DG VCXO, CLOCK, 10 MHz - 280 MHz, LVPECL OUTPUT
571AEB000164DG VCXO, CLOCK, 10 MHz - 810 MHz, LVPECL OUTPUT
5G14E-150N-FREQ VCXO, CLOCK, 1 MHz - 50 MHz, CMOS/TTL OUTPUT
5G14F-150M-FREQ VCXO, CLOCK, 1 MHz - 50 MHz, CMOS/TTL OUTPUT
5G42B-80M-FREQ VCXO, CLOCK, 1 MHz - 50 MHz, HCMOS/TTL OUTPUT
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