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參數(shù)資料
| 型號： | 5962-87702032C |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 195K |
| 代理商： | 5962-87702032C |
MAX4675/MAX4676
3
Single SPST Analog Switches
_______________________________________________________________________________________
7
Applications Information
Overvoltage Protection
Proper power-supply sequencing is recommended for all
CMOS devices. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can
cause permanent damage to the devices. Always
sequence V+ on first, then V-, followed by the logic
inputs, NO, NC, or COM. If proper power-supply
sequencing is not possible, add two small-signal diodes
(D1, D2) in series with the supply pins (Figure 1). Adding
diodes reduces the analog signal range to one diode
drop below V+ and one diode drop above V- but does
not affect the devices’ low switch resistance and low
leakage characteristics. Device operation is unchanged,
and the difference between V+ and V- should not
exceed 12V.
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1F capacitor connect-
ed from V+ to GND is adequate for most applications.
V+
V-
Vg
Figure 1. Overvoltage Protection Using External Blocking
Diodes
tr < 20ns
tf < 20ns
50%
0
LOGIC
INPUT
RL
300
COM
GND
V-
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VCOM
(
RL
)
RL + RON
SWITCH
INPUT
IN
+3V
tOFF
0
NO
OR NC
SWITCH
OUTPUT
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
35pF
V+
VOUT
MAX4675
MAX4676
Figure 2. Switching Time
Timing Diagrams/Test Circuits
Figure 3. Charge Injection
VGEN
GND
COM
CL
VOUT
V-
V+
VOUT
IN
OFF
ON
OFF
VOUT
Q = (
VOUT)(CL)
NC
OR NO
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
VIN = 3.0V
V+
RGEN
IN
MAX4675
MAX4676
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