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參數資料
| 型號： | 5962-8875701EA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 38 MHz, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 23/32頁 |
| 文件大?。?/td> | 687K |
| 代理商： | 5962-8875701EA |
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3
General Description
VCO
The VCO requires one external capacitor C1 (between C1A
and C1B) and one external resistor R1 (between R1 and
GND) or two external resistors R1 and R2 (between R1 and
GND, and R2 and GND). Resistor R1 and capacitor C1
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplies the design
of low-pass lters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
lter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEMOUT). In contrast to conventional
techniques where the DEMOUT voltage is one threshold
voltage lower than the VCO input voltage, here the DEMOUT
voltage equals that of the VCO input. If DEMOUT is used, a
load resistor (RS) should be connected from DEMOUT to
GND; if unused, DEMOUT should be left open. The VCO
output (VCOOUT) can be connected directly to the
comparator input (COMPIN), or connected via a frequency-
divider. The VCO output signal has a specied duty factor of
50%. A LOW level at the inhibit input (INH) enables the VCO
and demodulator, while a HIGH level turns both off to
minimize standby power consumption.
Phase Comparators
The signal input (SIGIN) can be directly coupled to the self-
biasing amplier at pin 14, provided that the signal swing is
between
the
standard
HC
family
input
logic
levels.
Capacitive coupling is required for signals with smaller
swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (fi) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is suppressed, is:
VDEMOUT =(VCC/π)(φSIGIN - φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT =VPC1OUT
(via low-pass lter).
The average output voltage from PC1, fed to the VCO input
via the low-pass lter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of signals (SIGIN) and the comparator input (COMPIN)as
shown in Figure 2. The average of VDEM is equal to 1/2
VCC when there is no signal or noise at SIGIN, and with this
input the VCO oscillates at the center frequency (fo).
Typical waveforms for the PC1 loop locked at fo are shown
in Figure 3.
FIGURE 1. LOGIC DIAGRAM
DEMOUT
R2
12
R1
R5
11
10
C1
R3
C2
PC2OUT
13
p
n
GND
VCC
PCPOUT
1
15
2
PC3OUT
PC1OUT
DOWN
RD
Q
D
CP
RD
Q
D
CP
UP
V
CC
VCC
RD
Q
SD
INH
59
VCOIN
VCO
-
+
VCO
OUT
COMPIN
-
+
SIGIN
C1B
C1A
VREF
R2
R1
67 4
3
14
-
+
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
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