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參數(shù)資料
| 型號(hào)： | 5962G9654001QXC |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 封裝： | BOTTOM-BRAZED, CERAMIC, DFP-16 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 233K |
| 代理商： | 5962G9654001QXC |
1
Standard Products
UT54ACS109/UT54ACTS109
Dual J-K Flip-Flops
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS109 - SMD 5962-96540
UT54ACTS109 - SMD 5962-96541
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K positive
triggered flip-flops. A low level at the preset or clear inputs sets
or resets the outputs regardless of the other input levels. When
preset and clear are inactive (high), data at the J and K input
meeting the setup time requirements are transferred to the out-
puts on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55
°C to +125°C.
FUNCTION TABLE
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
LOGIC SYMBOL
INPUTS
OUTPUT
PRE
CLR
CLK
J
K
Q
L
H
X
H
L
H
L
X
L
H
L
X
H 1
H
↑
L
H
↑
H
L
Toggle
H
↑
L
H
No Change
H
↑
H
L
H
L
X
No Change
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J
K1
CLK1
PRE1
Q1
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
8
9
VSS
Q2
Q1
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J1
K1
CLK1
PRE1
Q1
VSS
Q1
89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q1
(6)
(7)
Q1
Q2
(10)
(9)
Q2
(5)
PRE1
(4)
CLK1
(1)
CLR1
(11)
PRE2
(14)
J2
(12)
CLK2
(13)
K2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
S
C1
R
(2)
J1
(3)
K1
(15)
CLR2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962H9654001VXX | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 5962G9654003VXC | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 5962H9654002QXA | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 5962H9654002QXX | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 5962H9654002VXC | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
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