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| 型號： | 61SP6464 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 64 SYNCHRONOU擰管道靜態(tài)RAM |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 130K |
| 代理商： | 61SP6464 |
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
9
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117 MHz
Min.
-100 MHz
Min.
Symbol
Parameter
Max.
Max.
Unit
t
KC
Cycle Time
9.2
—
10
—
ns
t
KH
Clock High Time
3.4
—
4
—
ns
t
KL
Clock Low Time
3.4
—
4
—
ns
t
KQ
Clock Access Time
—
5
—
5
ns
t
KQX
(1)
Clock High to Output Invalid
1.5
—
2.5
—
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
—
0
—
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
5
2
5
ns
t
OEQ
Output Enable to Output Valid
—
5
—
5
ns
t
OEQX
(1)
Output Disable to Output Invalid
0
—
0
—
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
—
0
—
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
2
5
2
5
ns
t
AS
Address Setup Time
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
ns
t
AVS
Address Advance Setup Time
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
ns
t
AVH
Address Advance Hold Time
0.5
—
0.5
—
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
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