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參數資料
| 型號： | 62LV256SC |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 元件分類： | SRAM |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的128K的× 8位 |
| 文件頁數： | 5/9頁 |
| 文件大小： | 40K |
| 代理商： | 62LV256SC |
IS62LV256
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. K
12/11/02
5
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns
-70 ns
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Parameter
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
45
—
70
—
ns
Address Access Time
—
45
—
70
ns
Output Hold Time
2
—
2
—
ns
CE
Access Time
—
45
—
70
ns
OE
Access Time
—
25
—
35
ns
OE
to Low-Z Output
0
—
0
—
ns
OE
to High-Z Output
0
20
0
25
ns
CE
to Low-Z Output
3
—
3
—
ns
CE
to High-Z Output
0
20
0
25
ns
CE
to Power-Up
0
—
0
—
ns
CE
to Power-Down
—
30
—
50
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
1213
100 pF
Including
jig and
scope
1378
OUTPUT
3.3V
1213
5 pF
Including
jig and
scope
1378
OUTPUT
3.3V
Figures 1a
Figures 1b
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